Matt Guthaus
732f35a362
Change channel router to route from bottom up to simplify code.
2018-11-11 12:25:53 -08:00
Matt Guthaus
791d74f63a
Fix wrong exception handling that depended on order. Replaced with if/else instead.
2018-11-11 12:02:42 -08:00
Matt Guthaus
de61630962
Expand blocked pins to neighbor grid cells.
2018-11-09 14:25:10 -08:00
Matt Guthaus
31eff6f24e
Merge branch 'dev' into multiport_layout
2018-11-08 18:00:28 -08:00
Matt Guthaus
fd5cd675ac
Horizontal increments top down.
2018-11-08 17:01:57 -08:00
Matt Guthaus
e28978180f
Vertical channel routes go from left right. Horizontal go bottom up.
2018-11-08 16:49:02 -08:00
Matt Guthaus
7b10e3bfec
Convert port index lists to three simple lists.
2018-11-08 12:19:40 -08:00
Michael Timothy Grimes
7c3375fd4b
Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport
2018-11-08 09:59:52 -08:00
Matt Guthaus
f04e76a54f
Allow multiple must-connect pins with the same label.
2018-11-07 13:05:13 -08:00
Matt Guthaus
8d753b5ac7
Primitive cells only keep the largest pin shape.
2018-11-07 11:58:31 -08:00
Matt Guthaus
1fe767343e
Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup.
2018-11-07 11:31:44 -08:00
Michael Timothy Grimes
3c9821991b
Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport
2018-11-05 08:56:19 -08:00
Matt Guthaus
74c3de2812
Remove diagonal routing bug. Cleanup.
2018-11-02 14:57:40 -07:00
Matt Guthaus
866eaa8b02
Add debug message when routes are diagonal.
2018-11-02 11:50:28 -07:00
Matt Guthaus
b24c8a42a1
Remove redundant pins in pin_group constructor. Clean up some code and comments.
2018-11-01 11:31:24 -07:00
Michael Timothy Grimes
dc96d86082
Optimizations to pbitcell spacings
2018-11-01 07:58:20 -07:00
Matt Guthaus
c511d886bf
Added new enclosure connector algorithm using edge sorting.
2018-10-31 15:35:39 -07:00
Matt Guthaus
fc45242ccb
Allow contains to contain copy. Add connectors when pin doesn't overlap grids.
2018-10-30 17:41:29 -07:00
Matt Guthaus
6990773ea1
Add error check requiring non-zero area pin layouts.
2018-10-29 10:32:42 -07:00
Matt Guthaus
0107e1c050
Reduce verbosity of utils
2018-10-26 13:02:31 -07:00
Matt Guthaus
7d74d34c53
Fix pin_layout contains bug
2018-10-26 10:40:43 -07:00
Matt Guthaus
94e5050513
Move overlap functions to pin_layout
2018-10-24 16:13:07 -07:00
Matt Guthaus
dc73e8cb60
Odd bug that instances were not properly rotated.
2018-10-24 16:12:27 -07:00
Hunter Nichols
a711a5823d
Merged dev and fix conflicts in geometry.py
2018-10-24 10:52:22 -07:00
Hunter Nichols
53cb4e7f5e
Fixed lib files to be syntactically correct with multiport. Fixed issue in geometry.py that prevented netlist_only option from working.
2018-10-22 23:33:01 -07:00
Hunter Nichols
62439bdac6
Fixed merge conflicts with sram.py
2018-10-22 17:29:14 -07:00
Hunter Nichols
4f08062268
Added custom 1rw+1r bitcell. Testing are currently failing.
2018-10-22 17:02:21 -07:00
Michael Timothy Grimes
cda2e93cd7
Adding fix to netlist_only mode in geometry.py. Uncommenting functional tests and running both tests in netlist_only mode.
2018-10-22 09:17:03 -07:00
Matt Guthaus
0aad61892b
Supply router working except for off by one rail via error
2018-10-19 14:21:03 -07:00
Matt Guthaus
4bf1e206e2
Merge branch 'dev' into supply_routing
2018-10-17 09:47:18 -07:00
Matt Guthaus
e2cfd382b9
Fix print check regression
2018-10-15 13:23:31 -07:00
Michael Timothy Grimes
c8c70401ae
Redesign of pbitcell for newer process technolgies.
2018-10-15 06:29:51 -07:00
Matt Guthaus
ce8c2d983d
Update all drc usages to call function type
2018-10-12 14:37:51 -07:00
Matt Guthaus
4932d83afc
Add design rules classes for complex design rules
2018-10-12 09:44:36 -07:00
Matt Guthaus
9bb1c2bbcf
Fix Future Warning for real
2018-10-10 15:58:16 -07:00
Matt Guthaus
fa4dd8881c
Fix Future warnings comparison to None
2018-10-10 15:47:14 -07:00
Matt Guthaus
6bbf66d55b
Rewrote pin enclosure code to better address off grid pins.
...
Include only maximal pin enclosure shapes.
Add smallest area connector for off grid pins.
Fix decoder to use add_power_pin code.
Change permissions.
2018-10-10 15:15:58 -07:00
Matt Guthaus
a2b1d025ab
Merge multiport
2018-10-08 11:45:50 -07:00
Matt Guthaus
3244e01ca1
Add copy power pin function
2018-10-08 09:56:39 -07:00
Michael Timothy Grimes
6ef1a3c755
Improvements to functional test. Now will read or write in a random sequence, using randomly generated words and addresses, and using random ports in the multiported cases. Functional test still has some bugs that are being worked out so it will sometimes fail and sometimes not fail.
2018-10-08 06:34:36 -07:00
Matt Guthaus
8499983cc2
Add supply router to top-level SRAM. Change get_pins to elegantly fail.
2018-10-06 08:30:38 -07:00
Matt Guthaus
985d04d4b5
Cleanup of router.
...
Made offsets in geometry snap to grid.
Changed gds_write to use list for visited flag.
Rewrite self.gds each call in case of any changes.
2018-10-04 14:04:29 -07:00
Michael Timothy Grimes
34d8a19871
Adding simulation.py for common functions between functional and delay tests. Updating functional test.
2018-10-04 09:29:44 -07:00
Michael Timothy Grimes
a71486e22f
Adding mutliport constants to design.py to reduce the need for copied code across multiple modules.
2018-09-28 00:11:39 -07:00
Matt Guthaus
9b0142d6b9
Comment debug for possible performance issue
2018-09-24 11:44:32 -07:00
Matt Guthaus
87502374c5
DRC clean supply grid routing on control logic.
2018-09-20 16:00:13 -07:00
Matt Guthaus
fd9ffe30d6
Add layer width options to route object
...
Modify router to use track-width routes.
2018-09-18 15:12:53 -07:00
Matt Guthaus
8d2804b9cb
Supply router working except:
...
Off grid pins. Some pins do now span enough of the routing track and must be patched.
Route track width. Instead of minimum width route, it should be the track width.
2018-09-18 12:57:39 -07:00
Matt Guthaus
60cceab50a
Merge branch 'dev' into supply_routing
2018-09-17 11:34:31 -07:00
Matt Guthaus
a3c2b4384a
Improve comments. Simplify function interface for channel route.
2018-09-11 15:53:12 -07:00