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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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8499983cc2bf13d30924698d713aff4326f61b65
OpenRAM/compiler/base
T
History
Matt Guthaus 8499983cc2 Add supply router to top-level SRAM. Change get_pins to elegantly fail.
2018-10-06 08:30:38 -07:00
..
contact.py
Remove unique id in contact that was used for debugging
2018-09-04 16:40:52 -07:00
design.py
Cleanup of router.
2018-10-04 14:04:29 -07:00
geometry.py
Cleanup of router.
2018-10-04 14:04:29 -07:00
hierarchy_design.py
Update router to work with pin_layout structure.
2018-08-29 15:34:45 -07:00
hierarchy_layout.py
Add supply router to top-level SRAM. Change get_pins to elegantly fail.
2018-10-06 08:30:38 -07:00
hierarchy_spice.py
Update router to work with pin_layout structure.
2018-08-29 15:34:45 -07:00
lef.py
Remove carriage returns form python files
2018-08-07 09:44:01 -07:00
path.py
Merge branch 'dev' of github.com:mguthaus/OpenRAM into dev
2018-02-09 10:25:28 -08:00
pin_layout.py
DRC clean supply grid routing on control logic.
2018-09-20 16:00:13 -07:00
route.py
Add layer width options to route object
2018-09-18 15:12:53 -07:00
utils.py
Update router to work with pin_layout structure.
2018-08-29 15:34:45 -07:00
vector.py
Routing and connecting rails with vias done.
2018-09-07 14:46:58 -07:00
verilog.py
Move last few modules to base dir
2018-02-09 10:29:37 -08:00
wire.py
Merge branch 'dev' of github.com:mguthaus/OpenRAM into dev
2018-02-09 10:25:28 -08:00
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