Hunter Nichols 4f08062268 Added custom 1rw+1r bitcell. Testing are currently failing.

2018-10-22 17:02:21 -07:00

..

contact.py

Remove unique id in contact that was used for debugging

2018-09-04 16:40:52 -07:00

design.py

Improvements to functional test. Now will read or write in a random sequence, using randomly generated words and addresses, and using random ports in the multiported cases. Functional test still has some bugs that are being worked out so it will sometimes fail and sometimes not fail.

2018-10-08 06:34:36 -07:00

geometry.py

Add back LEF blockages. Remove "absolute" flags from GDS output

2018-09-05 09:28:43 -07:00

hierarchy_design.py

Update router to work with pin_layout structure.

2018-08-29 15:34:45 -07:00

hierarchy_layout.py

Comment debug for possible performance issue

2018-09-24 11:44:32 -07:00

hierarchy_spice.py

Update router to work with pin_layout structure.

2018-08-29 15:34:45 -07:00

lef.py

Remove carriage returns form python files

2018-08-07 09:44:01 -07:00

path.py

Merge branch 'dev' of github.com:mguthaus/OpenRAM into dev

2018-02-09 10:25:28 -08:00

pin_layout.py

Add inflate blockages and remove pins from blockages.

2018-09-05 11:06:17 -07:00

route.py

Update router to work with pin_layout structure.

2018-08-29 15:34:45 -07:00

utils.py

Added custom 1rw+1r bitcell. Testing are currently failing.

2018-10-22 17:02:21 -07:00

vector.py

Organize top-level files into subdirs.

2018-02-09 10:25:24 -08:00

verilog.py

Move last few modules to base dir

2018-02-09 10:29:37 -08:00

wire.py

Merge branch 'dev' of github.com:mguthaus/OpenRAM into dev

2018-02-09 10:25:28 -08:00