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OpenRAM
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496 Commits

Author SHA1 Message Date
Jesse Cirimelli-Low 03c5a58758 add sp non cypress bitcells 2026-05-04 12:47:00 -07:00
Jesse Cirimelli-Low a5c879f510 Merge remote-tracking branch 'openram_local/array_gen' into merge/full-array-gen-into-dev 
# Conflicts:
#	technology/sky130/custom/sky130_col_cap_array.py
 2026-04-30 12:43:19 -07:00
Jesse Cirimelli-Low 2780fda35c all sky130 crba passing 2026-04-28 23:22:40 -07:00
Jesse Cirimelli-Low 88241ca685 add fix for cypress sp wls 2026-04-28 17:19:54 -07:00
Jesse Cirimelli-Low c7f3ac33cd sky130 cypress dp working with offset relative to crba 2026-04-27 17:24:13 -07:00
Jesse Cirimelli-Low cb7f117daa squash commits 2026-04-22 01:33:47 -07:00
Jesse Cirimelli-Low 515591a422 dual port rba lvs clean again with cell library changes 2026-04-14 14:48:26 -07:00
Jesse Cirimelli-Low b6d98c44d5 singleport cba passing on both tech files 2026-03-17 14:50:43 -07:00
Jesse Cirimelli-Low ffcbd51019 technology switching working 2026-03-17 11:44:20 -07:00
Jesse Cirimelli-Low ab33017fe2
Merge pull request #282 from ruhai-lin/stable 
Attempt to fix LVS mismatch and SRAM creation with banks for sky130
 2026-03-12 10:47:23 -07:00
rlin50 ec28bc6dfd Fix sky130 1rw LVS mismatch by correcting col_cap pin order 2026-02-22 22:11:35 -08:00
Jesse Cirimelli-Low 53d53ec271 checkpoint from tt submission 2026-01-14 12:08:26 -08:00
Vikash Patel b9bb6898af Fix for Missing lef_rom_interconnect in tech.py 2025-10-17 14:40:03 +05:30
Jesse Cirimelli-Low 5a74605117 single port fixes 2025-09-12 11:25:03 -07:00
Jesse Cirimelli-Low 4ce6e0538b fix col_cap array for dummu compatability ...bitcells next 2025-03-06 02:05:43 -08:00
Jesse Cirimelli-Low f3c1c5fbb2 Merge branch 'singleport_refactor' into array_gen 2025-02-24 23:26:28 -08:00
mrg 3f1f58065d Add nand4 leakage to sky130 tech 2024-07-01 10:14:43 -07:00
mole99 85e242fa27 Add gf180mcu ROM example 2024-02-03 11:31:58 +01:00
Hadir Khan bd9ebc3300 updated the spice file 2023-10-31 23:24:21 -07:00
hadirkhan10 561e0c228c updated the cell name for layout and schematic 2023-10-31 23:24:21 -07:00
hadirkhan10 4b4153bdea renamed the gds and sp file to reflect the cell name 2023-10-31 23:24:21 -07:00
hadirkhan10 98a4210b06 added the gds and spice of the bitcell 2023-10-31 23:24:21 -07:00
hadirkhan10 042bfcabea added the custom cell definition 2023-10-31 23:24:21 -07:00
Hadir Khan b65ebc6160 corrected the import statement and removed strap variant attribute which is no longer needed 2023-10-31 23:24:21 -07:00
SWalker 565e3f6814 flatten ptx in extraction and renumber test based on importance 2023-10-31 23:24:21 -07:00
SWalker 3271c5e73c fixing drc on rom bank, mostly spacing tweaks 2023-10-31 23:24:21 -07:00
SWalker 75f7a5847f fixing contact placement for gf180 in rom 2023-10-31 23:24:21 -07:00
SWalker a544abebf7 fixed contact area issue 2023-10-31 23:24:21 -07:00
SWalker 20d0df2947 more boundary on the other side 2023-10-31 23:24:21 -07:00
Sage Walker cb8567c66f spacing tweaks for gf180 address control gate 2023-10-31 23:24:21 -07:00
SWalker d940c0e03d little more boundary 2023-10-31 23:24:21 -07:00
SWalker 23611f8fac little more nwell 2023-10-31 23:24:21 -07:00
SWalker e3b51360f3 extend nwell on nand 2023-10-31 23:24:21 -07:00
SWalker ea703d124f switched input pins on nand 2023-10-31 23:24:21 -07:00
SWalker 07fa78e00c boundary shift for implant spacing 2023-10-31 23:24:21 -07:00
SWalker dba75fc57c boundary and alignment of nand 2023-10-31 23:24:21 -07:00
SWalker 9ac94d1744 even more nand 2023-10-31 23:24:21 -07:00
SWalker 0aa9c47f89 more nand 2023-10-31 23:24:21 -07:00
SWalker 8ac30f4ef5 proper gds for nand 2023-10-31 23:24:21 -07:00
SWalker 416140d04a nand dup pin 2023-10-31 23:24:21 -07:00
SWalker 8c56478df3 more nand tweaks 2023-10-31 23:24:21 -07:00
SWalker 13459cb6dd boundary box tweaks on dec nand 2023-10-31 23:24:21 -07:00
SWalker 88782b0a58 rotated nand2_dec 2023-10-31 23:24:21 -07:00
SWalker 4bb586c949 decoder nand custom cell 2023-10-31 23:24:21 -07:00
Sage Walker d6cb15c82d Switched to GF180D for extra metal layers, Fixed drc parameters so contacts are valid. ptx.py modified to achieve proper layer placement with gf180. ROM array and precharge DRC clean. 2023-10-31 23:24:21 -07:00
Hadir Khan 698020301c updates to add the port order overwrite attribute, ignore drc/lvs attribute and pwell as a non-routing layer 2023-10-31 23:24:21 -07:00
hadirkhan10 b9fd172e44 corrected the pin mapping 2023-10-31 23:24:21 -07:00
hadirkhan10 de7a248ff0 added the cell property definitions 2023-10-31 23:24:21 -07:00
Jesse Cirimelli-Low a904874978 passing gf180 parameterized gate tests 2023-10-31 23:24:21 -07:00
Jesse Cirimelli-Low d18a4f8c7c additional tech commits 2023-10-31 23:24:21 -07:00