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OpenRAM
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2,464 Commits 4 Branches 63 Tags 78 MiB
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2114 Commits

Author SHA1 Message Date
mrg 4b526f0d5f Check min size inverter. 2020-05-13 16:54:26 -07:00
mrg f8bcc54338 Determine width after routing with no well contacts. 2020-05-13 16:04:38 -07:00
mrg 617bf302d1 Add option to remove wells. Save area in pgates with redundant wells. 2020-05-13 14:46:42 -07:00
mrg 848241a3ad PEP8 cleanup 2020-05-11 16:22:17 -07:00
mrg c96a6d0b9d Add no well option. Add stack gates vertical option. 2020-05-11 16:22:08 -07:00
mrg b7c66d7e07 Changes to simplify metal preferred directions and pitches. 
Changes to allow decoder height to be a 2x multiple of bitcell height.
Split of control logic tests.
Fixed track spacing in SRAM and channel router
PEP8 cleanup.
 2020-05-10 11:32:45 -07:00
mrg dd73afc983 Changes to allow decoder height to be a 2x multiple of bitcell height. 
Convert to use li layer in pgates.
Fix multifinger devices with li layers.
Simplify wordline driver input routing.
Fix power pin direction option update.
PEP8 cleanup
Changes to simplify metal preferred directions and pitches.
Split of control logic tests.
 2020-05-10 06:56:22 -07:00
jcirimel 5666e79287 Merge branch 'dev' into discrete_models 2020-05-08 03:13:16 -07:00
jcirimel d8a51ecafb remove prints, scaling bug fix 2020-05-05 21:59:28 -07:00
jcirimel 71a1dd8f38 fix tx binning in col mux for memories with >1 word per row 2020-05-05 16:35:51 -07:00
Joey Kunzler 0bae652be9 fix merge conflicts 2020-04-23 11:51:46 -07:00
Joey Kunzler fed1c0bbe1 s8 col mux array 2020-04-22 16:22:34 -07:00
mrg 32576fb62c Convert wordline driver to pand2 rather than pnand2+pdriver 2020-04-22 13:27:50 -07:00
mrg 8e243f1b3c Merge branch 'dev' into tech_migration 2020-04-22 11:34:14 -07:00
Matt Guthaus fb17abb16c Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-04-22 10:40:27 -07:00
Matt Guthaus 14f440df73 Update golden results with new lib syntax 2020-04-22 10:40:04 -07:00
mrg 4d6d6af0a1 Merge remote-tracking branch 'public/dev' into dev 2020-04-22 09:28:25 -07:00
David Ratchkov c2419af2e2 Fix voltage_map names (these do not need to match pg_pin names) 2020-04-22 09:03:22 -07:00
Joey Kunzler 60ba2c1aa5 updated pbitcell test names 2020-04-21 17:20:29 -07:00
mrg 0bb4a7f93d Merge branch 'dev' into tech_migration 2020-04-21 16:37:36 -07:00
mrg f1c1adc9bd Simplify supply contacts in delay chain. 2020-04-21 16:12:54 -07:00
Joey Kunzler 3d4a40b338 freepdk45 col_mux fix 2020-04-21 15:38:19 -07:00
mrg 0f6998a1c5 PEP8 cleanup 2020-04-21 15:36:38 -07:00
mrg fc85dfe29f Add boundary to all pgates 2020-04-21 15:21:57 -07:00
mrg cd66ddb37c Add supply rails to dff array. PEP8 cleanup. 2020-04-21 15:21:29 -07:00
mrg ab91d0ab1d Add purpose to string output 2020-04-21 15:20:30 -07:00
Joey Kunzler ee1de9ac8c Merge branch 's8_update' of github.com:VLSIDA/PrivateRAM into s8_update 2020-04-20 22:14:09 -07:00
Joey Kunzler 829f3e03fa col_mux.py update with correct contacts 2020-04-20 22:08:29 -07:00
Joey Kunzler 63bea67fb5 col_mux.py changes 2020-04-20 20:22:46 -07:00
mrg f6135f3471 PEP8 formatting 2020-04-20 16:38:30 -07:00
mrg 90fdaf902c Merge branch 'tech_migration' into dev 2020-04-20 16:28:16 -07:00
mrg dfbf6fe45c Default is to use preferred layer directions 2020-04-20 15:33:53 -07:00
mrg 8c177f9947 Split col mux test 2020-04-20 15:03:32 -07:00
mrg 7995451cbb PEP8 formatting 2020-04-20 14:45:18 -07:00
mrg 69d0e5e372 Split port data test into single and multi-port. 2020-04-20 14:26:44 -07:00
mrg 7f65176908 Configured bitline directions into prot_data 2020-04-20 14:23:40 -07:00
mrg 2a9dde5401 Merge branch 'tech_migration' into dev 2020-04-20 09:07:36 -07:00
jcirimel 32317ce3a5 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into dev 2020-04-18 14:23:31 -07:00
jcirimel f590ecf83c fix minimum pinv sizing 2020-04-18 05:51:21 -07:00
jcirimel add9ec7b28 remove excess newlines 2020-04-18 05:42:23 -07:00
jcirimel 85bc801689 fix pinv drc bug 2020-04-18 05:34:55 -07:00
jcirimel 1f094b03bc use more optimal discrete pinv sizing 2020-04-18 05:26:39 -07:00
David Ratchkov 5aea45ed69 - Fix switched disabled powers 2020-04-17 16:23:06 -07:00
David Ratchkov 123cc371be - Fix disabled power char 2020-04-17 16:09:58 -07:00
jcirimel 486819ae0d fix width bin typo 2020-04-17 15:27:36 -07:00
David Ratchkov 1f816e2823 - Characterize actual disabled power (read mode only) 
- Report rise/fall power individually
 2020-04-17 14:55:17 -07:00
jcirimel a158ad1e81 add missing import 2020-04-17 14:24:52 -07:00
mrg cbb67ad483 Update to run LVS when no DRC errors too. 2020-04-17 13:57:52 -07:00
David Ratchkov 7e36cd4828 - Write voltage_map and pg_pin 
- Remove 'when' condition on leakage power
- Remove 'clk*' from 'when' condition on internal_power on the same 'clk*' pin
 2020-04-17 13:45:57 -07:00
Joey Kunzler 7920b0cef9 m3 min area rounding fix 2020-04-17 12:36:48 -07:00