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OpenRAM
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1107 Commits

Author SHA1 Message Date
Jesse Cirimelli-Low 29f19ad70f replaced absolute links with relative links 2018-11-20 12:27:54 -08:00
Jesse Cirimelli-Low 7d070c2652 Added links to logos 2018-11-20 11:51:38 -08:00
Jesse Cirimelli-Low 1942ef33ac Merge branch 'dev' into datasheet_gen 2018-11-20 11:23:42 -08:00
Matt Guthaus b8299565eb Use grid furthest from blockages when blocked pin. Enclose multiple connectors. 2018-11-19 17:32:55 -08:00
Matt Guthaus 20d4e390f6 Add bounding box of connector for when there are multiple connectors 2018-11-19 15:45:07 -08:00
Matt Guthaus 2694ee1a4c Add all insufficient grids that overlap the pin at all 2018-11-19 15:43:19 -08:00
Matt Guthaus a47509de26 Move via away from cell edges 2018-11-19 15:42:22 -08:00
Matt Guthaus 6a7d721562 Add new bbox routine for pin enclosures 2018-11-19 09:28:29 -08:00
Matt Guthaus 4630f52de2 Use array ur instead of bank ur to pace row addr dff 2018-11-19 08:41:26 -08:00
Matt Guthaus 7709d5caa7 Move row addr dffs to top of bank to prevent addr route problems 2018-11-18 10:02:08 -08:00
Matt Guthaus ba8bec3f67 Two m1 pitches at top of control logic 2018-11-18 09:30:27 -08:00
Matt Guthaus c677efa217 Fix control logic center location. Fix rail height error in write only control logic. 2018-11-18 09:15:03 -08:00
Matt Guthaus 047d6ca2ef Must channel rout the column mux bits since they could overlap 2018-11-16 16:21:31 -08:00
Matt Guthaus b89c011e41 Add psram 1w/1r test. Fix bl/br port naming errors in bank. 2018-11-16 15:31:22 -08:00
Matt Guthaus 8f28f4fde5 Don't always add all 3 types of contorl. Add write and read only port lists. 2018-11-16 15:03:12 -08:00
Matt Guthaus b13d938ea8 Add m3m4 short hand in design class 2018-11-16 14:10:49 -08:00
Matt Guthaus 4997a20511 Must set library cell flag for netlist only mode as well 2018-11-16 13:37:17 -08:00
Matt Guthaus ca750b698a Uniquify bitcell array 2018-11-16 12:52:22 -08:00
Matt Guthaus e040fd12f9 Bitcell and bitcell array can be named the same. 2018-11-16 12:00:23 -08:00
Matt Guthaus 5e0eb609da Check for single top-level structure in vlsiLayout. Don't allow dff_inv and dff_buf to have same names. 2018-11-16 11:48:41 -08:00
Matt Guthaus 68ac7e5955 Fix offset of column decoder with new mirroring 2018-11-15 17:27:58 -08:00
Matt Guthaus 712b71c5ca Mirror port 1 column decoder in X and Y 2018-11-15 15:26:59 -08:00
Jesse Cirimelli-Low 59c0421804 merge dev into datasheet_gen; fixed merge conflict in hierarchy_design.py 2018-11-15 10:45:33 -08:00
Matt Guthaus 21d111acfe Move wordline driver clock line below decoder. Fix port 1 clock route DRC. 2018-11-15 10:30:38 -08:00
Matt Guthaus 66982a9283 Only add second port if it is specified. 2018-11-14 17:11:23 -08:00
Matt Guthaus 2fd86958a8 Merge branch 'multiport_layout' of ssh://scone/home/mrg/openram into multiport_layout 2018-11-14 17:07:01 -08:00
Matt Guthaus 3cfefa784f Fix run-time bug in combine adjacent pins for supply router 2018-11-14 17:06:12 -08:00
Matt Guthaus 3221d3e744 Add initial support and unit tests for 2 port SRAM 2018-11-14 17:05:23 -08:00
Matt Guthaus 6ac5adaeca Separate multiport replica bitline from regular replica bitline test 2018-11-14 11:41:09 -08:00
Matt Guthaus 2f6300c7a0 Fix date/time formatting to remove fraction seconds. 2018-11-14 10:31:33 -08:00
Matt Guthaus 18d874a96a Fix error in iterative implementation of combine_classes 2018-11-14 10:05:04 -08:00
Matt Guthaus 4ebb8a26c4 Disable debug statements. 2018-11-13 17:43:08 -08:00
Matt Guthaus ddb4cabfe1 Change recursive equivalence class detection to iterative. 2018-11-13 17:42:06 -08:00
Matt Guthaus ff0a7851b7 Fix error when DRC is disabled so it doesn't initialize. 2018-11-13 17:41:32 -08:00
Jesse Cirimelli-Low fa27d647d2 Flask directory upload POC, embed datasheet.info in html comment for parser reuse 2018-11-13 17:29:43 -08:00
Matt Guthaus ce74827f24 Add new option to enable inline checks at each level of hierarchy. Default is off. 2018-11-13 16:51:19 -08:00
Matt Guthaus 01ceedb348 Only check number of ports when doing layout. 2018-11-13 16:42:25 -08:00
Matt Guthaus bc7e74f571 Add multiport bank test 2018-11-13 16:06:21 -08:00
Matt Guthaus aa779a7f82 Initial two port bank in SCMOS 2018-11-13 16:05:22 -08:00
Matt Guthaus 732f35a362 Change channel router to route from bottom up to simplify code. 2018-11-11 12:25:53 -08:00
Matt Guthaus 791d74f63a Fix wrong exception handling that depended on order. Replaced with if/else instead. 2018-11-11 12:02:42 -08:00
Jesse Cirimelli-Low 0dd97e54dd reverted css to UCSC colors, fixed header styling, added placeholder openram logo 2018-11-11 09:27:07 -08:00
Jesse Cirimelli-Low 4227a7886a Merge branch 'dev' into datasheet_gen 2018-11-11 07:27:42 -08:00
Jesse Cirimelli-Low 91a63fb5c2 Merge branch 'dev' 2018-11-11 07:24:03 -08:00
Jesse Cirimelli-Low 5c4ee911aa added another VLSI logo and fixed control port numbering 2018-11-11 07:22:13 -08:00
Jesse Cirimelli-Low aadf160ce4 added missing space in sheet 2018-11-11 06:05:14 -08:00
Jesse Cirimelli-Low 4ba07e4b94 Complete rewrite of parser, all ports (except clock) added on multiport sheets 2018-11-10 20:23:26 -08:00
Matt Guthaus 5cbbd5e4ca Comment out regress CI debug code 2018-11-10 13:44:36 -08:00
Matt Guthaus 6c17734712 Add testutil archive on failed tests for debug 2018-11-10 11:54:28 -08:00
Jesse Cirimelli-Low 62f8d26ec6 Merge branch 'dev' into datasheet_gen 2018-11-10 10:58:35 -08:00