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643 Commits

Author SHA1 Message Date
Michael Timothy Grimes 19ca0d6c2a Changing control logic names to match naming scheme for multi-port. din[0] to din0[0], s_en to s_en0, addr[0] to addr0[0], etc. Sram level should pass unit tests for single port but will not currently pass for multi-port 2018-08-18 16:51:21 -07:00
Michael Timothy Grimes 0f8da1510e Reverting pin name changes of precharge cell and array back to 'bl' and 'br'. Also clarifying bl and br init parameters to reflect that they refer to the bitcell lines. 2018-08-18 15:27:07 -07:00
Michael Timothy Grimes e147f807a5 adding a unit test for multiported bank, this test will skip in the regression testing because multiported bank does not pass drc yet 2018-08-15 04:32:56 -07:00
Michael Timothy Grimes e4a94e8597 Merging changes to bank. Bank has been altered to accommodate multiport. Single port still passes unit test, though some control signal names have been changed to have a following 0 (e.g. s_en to s_en0). Multiport does not pass drc yet, but can accurately generate a spice netlist. 2018-08-15 04:00:48 -07:00
Michael Timothy Grimes e592d95146 Altered bank to accommodate multiport. Single port still works, though some of the control signal names have been changes to have a following 0 (e.g. s_en to s_en0). Multiport does not pass drc yet, but can generate an accurate spice netlist. 2018-08-15 03:36:40 -07:00
Michael Timothy Grimes a5af4a2b9c resolved variable name error in 00_code_format test 2018-08-15 03:33:33 -07:00
Michael Timothy Grimes af43fb6276 called bitcell function before reading the height of the bitcell because pbitcell's dynamic height can only be determined after the module is called 2018-08-15 02:19:36 -07:00
Michael Timothy Grimes 040340b49f editted naming convention on precharge to accommodate multiport 2018-08-15 02:14:45 -07:00
Michael Timothy Grimes 8d97862f6e altered precharge array and precharge unit tests to accommodate multiport 2018-08-15 00:55:23 -07:00
Matt Guthaus 36bfd2932a Update delay results with new clock routing 2018-08-14 10:51:02 -07:00
Matt Guthaus 8900edbe12 Finalize single bank clock routing. 2018-08-14 10:36:35 -07:00
Matt Guthaus 3420b1002c Connect data and column DFF clocks in 1 bank. 2018-08-14 10:09:41 -07:00
Matt Guthaus 5ff49d322d bank_sel_bar only used for clk now 2018-08-13 15:14:52 -07:00
Matt Guthaus f7f318d72e Remove tri_en signals from bank control logic. 2018-08-13 14:47:03 -07:00
Matt Guthaus 49bee6a96e Remove OEB signal since we split DIN/DOUT ports 2018-08-13 14:09:49 -07:00
Matt Guthaus 9ffba4b052 Add +x permissions on precharge and pbitcell tests 2018-08-13 09:57:10 -07:00
Matt Guthaus 34736b7b3f Remove carriage returns form python files 2018-08-07 09:44:01 -07:00
Matt Guthaus abacf6a2d0 Add carriage return check for python files 2018-08-07 09:40:45 -07:00
Michael Timothy Grimes c2a9e91dba Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-08-05 19:53:28 -07:00
Michael Timothy Grimes 5666ee6635 altered precharge module to accomodate bitlines from pbitcell, and altered unit test to test both bitcell and pbitcell configurations 2018-08-05 19:46:05 -07:00
Michael Timothy Grimes ecd4612167 altered bitcell, pbitcell, and bitcell array modules to accomodate additional bitline reference functions 2018-08-05 19:43:59 -07:00
Matt Guthaus c0d5f781cf Not sure how VCG channel constraint got removed. Fixed this bug before... 2018-07-27 15:15:40 -07:00
Matt Guthaus a7a3099702 Fix comments in stimulus file to show list and not zip type 2018-07-27 15:00:00 -07:00
Matt Guthaus d739c17b8d Fix delay numbers in hspice delay unit test. 2018-07-27 14:43:52 -07:00
Matt Guthaus d75d17bc8a Update golden results for FreePDK45 tests. 2018-07-27 14:25:52 -07:00
Matt Guthaus 642a5cfe73 Line-wrap pinv debug formatting 2018-07-27 14:07:55 -07:00
Matt Guthaus 71606e1097 Add read cycle to clear DOUT bus before each read measure. 2018-07-27 14:06:59 -07:00
Matt Guthaus 8f72621f4a Converted delay measurement to use add_read/add_write functions. 
Rewrote the logic to add one cycle at a time for easier
manipulation. This can be extended more easily into the
functional simulations.
 2018-07-27 11:36:17 -07:00
Matt Guthaus 5b2cb6a95e Update remaining SCMOS golden lib files. 2018-07-27 09:44:12 -07:00
Matt Guthaus 6b967c08dd Updated output messages in timing test comparisons. 
Added output to show which lines differ and what their line numbers are..
Added output to show relative difference of approximate compares.
Added output to include file names that mismatch.
 2018-07-27 09:34:44 -07:00
Matt Guthaus 01cbc71a2a Limit sizes for dff_buf too. Add comments about restriction. 2018-07-27 08:17:50 -07:00
Matt Guthaus b541efe959 Fix wide gnd rail spacing to inverter NMOS by adding size limit to pinv. 2018-07-27 07:23:18 -07:00
Matt Guthaus 0e0516c4a6 Fix delay test unit test results. 2018-07-26 16:45:09 -07:00
Matt Guthaus 85595b0f6f Update format of delay test output during an error to directly 
copy into unit test. Factor function into testutils.py for comparison.
 2018-07-26 16:05:24 -07:00
Matt Guthaus 5088487cf7 Update delay tests to output useful information for debug. 2018-07-26 15:45:17 -07:00
Matt Guthaus a00e160274 Convert bitline index to integer in trim_spice 2018-07-26 14:29:44 -07:00
Matt Guthaus f098b995f0 Fix pinvbuf test to use new interface with only driver size. 2018-07-26 14:20:00 -07:00
Matt Guthaus c8808c268a Close output log in test 30 to avoid warning 2018-07-26 14:01:40 -07:00
Matt Guthaus bc67ad5ead Fixed timing to be measured from positive clock edge since 
reading a 1 will be the precharge time.
Started modifying the lib file for DIN and DOUT ports, but did not
check the syntax yet.
 2018-07-26 13:58:50 -07:00
Matt Guthaus e827c1b8c7 Make pinvbuf have unique names for GDS compliance. 
Add back gating of w_en since write should happen in second half
or else we will have write and precharge simultaneously active.
 2018-07-26 11:40:40 -07:00
Matt Guthaus 00a87d57ab Modified pinvbuf to have a stage effort of 4 for driving the 
clock bar to wordline enable.
Fixed comments in stimulus file to have right cycle numbers.
Removed clock gating on we signal since clock gating is already
done on the WL signals. It is redundant.
 2018-07-26 11:28:48 -07:00
Michael Timothy Grimes fb0de710ec Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-07-26 09:04:59 -07:00
Michael Timothy Grimes 27ab411146 fixed error I missed in pbitcell_array test 2018-07-26 09:02:52 -07:00
Matt Guthaus dd7069dd98 Remove print statement 2018-07-25 15:51:48 -07:00
Matt Guthaus b7525a14c2 Change DIN to DOUT in characterizer. Spacing dff flops down by m2 not m1 pitch. 2018-07-25 15:50:49 -07:00
Matt Guthaus d6df215718 Always use m2_pitch as default for channel for via spacing rules 2018-07-25 15:47:11 -07:00
Matt Guthaus 6d71c3f790 Fix bug to remove pin from conflicts in addition to graph keys 2018-07-25 15:36:16 -07:00
Matt Guthaus a4bfbe3545 Move dff_array pins to center of rail 2018-07-25 15:08:04 -07:00
Matt Guthaus 44f0e4a1de Fix new offset coordinate syntax error 2018-07-25 13:47:36 -07:00
Matt Guthaus 64b3cfee26 Only print LVS/DRC stats when it is enabled 2018-07-25 13:44:34 -07:00