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OpenRAM
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112 Commits

Author SHA1 Message Date
Matt Guthaus 269d553857 Move sense amp to tri gate routing to M3... not ideal. 2018-04-23 09:14:18 -07:00
Matt Guthaus 248decd004 Hand edit sense amp to have full pins rather than split from magic gds write. 2018-04-20 15:46:39 -07:00
Matt Guthaus c75eafe085 Fix some errors 2018-04-18 09:37:33 -07:00
Matt Guthaus 63a8f7c653 Remove m2 from write driver 2018-04-16 16:15:35 -07:00
Matt Guthaus 6640d3491d Tri gate and array supply to M2 and M3 2018-04-11 15:11:47 -07:00
Matt Guthaus 46c18f53ba Add M2 vias in ms_flop 2018-04-11 14:10:57 -07:00
Matt Guthaus 4f8ab78ee2 Change write driver supply pins to M2 2018-04-11 09:29:54 -07:00
Matt Guthaus a6c2e77bcf Move precharge and column mux cells to pgate directory. 
Move gnd to M3 in column mux.
Create column mux cell unit test.
 2018-04-06 17:15:14 -07:00
Matt Guthaus a0bf5345f8 Mostly working for 1 bank. 2018-03-23 08:14:26 -07:00
Matt Guthaus 1f81b24e96 Single bank passing DRC and LVS again. 
Unfold hierarchical decoder to improve routability.
 2018-03-23 08:13:10 -07:00
Matt Guthaus 8d9b79dfd8 Add dff_buf for buffered flop arrays. 2018-03-04 16:13:10 -08:00
Matt Guthaus fc441fe568 Add LICENSE and README from NCSU CDK 2018-03-02 10:42:23 -08:00
Matt Guthaus 7293eb33bc Merge branch 'dev' of https://github.com/mguthaus/OpenRAM into dev 2018-03-02 10:30:16 -08:00
Matt Guthaus ae2dbb4cd5 Add display techfiles from NCSU PDKs. 2018-03-02 10:30:03 -08:00
Hunter Nichols d0dcd9f34b Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality. 2018-03-01 23:34:15 -08:00
Matt Guthaus 9a6081de0e Remove KP from SCMOS models to get rid of ngspice error. 2018-03-01 11:10:04 -08:00
Matt Guthaus 2b839d34a3 Get rid of netgen error of undefined dlatch. Fix sp_read to find correct subckt name and pins. 2018-02-27 08:59:46 -08:00
Matt Guthaus 9d1f31467e Move internal power to clock pin. Differentiate leakge power when CSb is high. 2018-02-23 12:21:32 -08:00
Matt Guthaus b31f3c18af Change BSIM3 models to version 3.3.0. Add comment about multithreading selection. 2018-02-21 17:50:12 -08:00
Matt Guthaus 9559421ca8 Connect dff array clk in rows and columns. 2018-02-14 16:46:26 -08:00
Matt Guthaus 2d87dcda46 dff array done except for clock net 2018-02-14 16:03:29 -08:00
Matt Guthaus 0804a1eceb Add new DFF. Create DFF module. Start dff_array, not tested. 2018-02-14 15:16:28 -08:00
mguthaus 767990ca3b Update golden lib tests. Add new generic SCMOS models. Fix tech error with new msflop_in_cap name. 2018-02-13 15:54:50 -08:00
Matt Guthaus ccc8ed2b48 Add slow and fast SCMOS spice models. 2018-02-12 17:16:40 -08:00
mguthaus 6bf4190dde Fix missing tech name in path to spice models. Rename models to p,n. 2018-02-12 10:24:15 -08:00
Matt Guthaus a12ebeed9f Add multiple process corners. Unit tests use nominal corner only. Add fake SCMOS nominal models, but they are broken. 2018-02-12 09:33:23 -08:00
Matt Guthaus f86985821a Begin modifications for corner-based characterization. Made stimuli.py a class. Golden output files are not updated. 2018-02-09 15:33:03 -08:00
Matt Guthaus f4a99be9d8 Add poly_to_field_poly rule in SCMOS 2018-02-08 16:08:20 -08:00
Matt Guthaus 6f8744712d Add extra pwc to 6T SCMOS cell. 2018-02-05 14:44:15 -08:00
Matt Guthaus fb90b8f5fe Fix pin nameon sense amp spice. Fix NAND2 bug in hierarchical decoder. 2018-02-02 14:08:56 -08:00
Matt Guthaus 64546ad3dd Change wen to en in spice lib files. Check lvs report insted of stdout with netgen. 2018-02-01 05:38:48 -08:00
Matt Guthaus 512448f9e8 Fix pin names to lower case. Fix write driver DRC errors and LVS error. 2018-01-31 17:37:16 -08:00
Matt Guthaus 51a72e26c7 Fix via1 BL disconnect error. 2018-01-31 10:35:28 -08:00
Matt Guthaus 58da8af619 Make both gnd rails in 6T cell from top to bottom in SCMOS. Connect in bitcell array. 2018-01-31 10:04:28 -08:00
Matt Guthaus c63eb3be3b Fixed bug with missing tri gate via. 2018-01-29 17:29:30 -08:00
Matt Guthaus 8fcc8a1674 Increase height slightlty to allow pnand3 to pass DRC. 2018-01-29 15:30:58 -08:00
Matt Guthaus 1dc7752429 Fix 6T and replica cell contact spacing issues with Magic DRC. 
DRC/LVS passing for all parameterized gates.
Magic and GDS match for SCMOS rules again.
 2018-01-26 12:39:00 -08:00
Matt Guthaus fb0355ebaf Duplicate gnd label on metal1 pin in tri gate. 2018-01-24 13:20:34 -08:00
Matt Guthaus 039f531243 Capitalize bitline labels in write driver 2018-01-24 13:15:14 -08:00
Matt Guthaus d84242719b Change pin names in trigate and write_driver. 2018-01-24 13:12:36 -08:00
Matt Guthaus ac8eada0d8 Fix devices sizes in SCMOS sense amp. Elaborate magic/netgen scripts in comments. 2018-01-24 13:02:55 -08:00
Matt Guthaus 2468f224d9 SCMOS library cells passing LVS (with property errors though). Permute must be enabled before compare, duh. 2018-01-22 17:14:39 -08:00
Matt Guthaus fb2ed1d46c Add wells to fix DRC errors in SCMOS library cells. 2018-01-22 16:28:20 -08:00
Matt Guthaus efa465757c Remove dead code ptx_port. 2018-01-19 16:19:05 -08:00
Matt Guthaus 1701eac1a9 Added workaround to import layouts into Magic. Select and well layers in active contacts. Fixed missing implant enclose active DRC rule in parameterized cells. 2018-01-11 10:24:44 -08:00
Matt Guthaus e95988c639 Document tech files. Remove unused/redundant rules. Made rule names consistent/simple. 2018-01-08 11:57:51 -08:00
Matt Guthaus 8df46abb30 Move nmos gate to the top of the ptx. 2017-12-01 08:31:16 -08:00
Matt Guthaus 7ff82a2aed Improved ptx code but removed internal active/poly positions. 2017-11-28 18:13:32 -08:00
Matt Guthaus 257cd62d25 Remove tools from tech file and have search order preference like spice. 2017-11-14 15:27:03 -08:00
Matt Guthaus 3e0f39cd8e Skeleton code for indirect DRC/LVS/PEX tools. 2017-11-14 14:59:14 -08:00
Matt Guthaus e06e1691c8 Two bank SRAMs working in both technologies. 2017-09-29 16:22:13 -07:00
Matt Guthaus cf940fb15d Development version of new pin data structure. Tests pass LVS/DRC except for bank level. 2017-08-23 15:02:15 -07:00
Matt Guthaus 20d8c0bc45 Improved characterizer. 2017-07-06 08:42:25 -07:00
Matt Guthaus 34e180b901 Analytical delay model from Bin Wu. Unit test not passing. 2017-05-30 12:50:07 -07:00
mguthaus 7ca5c0b34f Added zoom to technology file so labels in each tech are readable size. Made default size. 2017-05-23 16:18:11 -07:00
Matt Guthaus fef708cffd Add slash in layers.map 2016-11-18 15:05:17 -08:00
Matt Guthaus 8934c1d3a4 Fixed layer map in runset files 2016-11-18 11:21:12 -08:00
Matt Guthaus b51c124810 Moved spice path to technology setup files instead of tech file itself. 2016-11-09 13:29:33 -08:00
Matt Guthaus 04949e093d Fixed path to non-distributable SCMOS spice models 2016-11-09 13:19:08 -08:00
Matt Guthaus db8a675d90 Clean up tech files to remove old parameters moved to premade cell classes. 2016-11-09 11:35:32 -08:00
Matt Guthaus b04e63dd65 Add back scn3me_subm rule files 2016-11-09 09:32:26 -08:00
Matt Guthaus f48272bde6 RELEASE 1.0 2016-11-08 09:57:35 -08:00