mirror of https://github.com/VLSIDA/OpenRAM.git
Add back scn3me_subm rule files
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////////////////////////////////////////////////////////////
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// DEFINE BOOLEAN LAYERS
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////////////////////////////////////////////////////////////
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LAYOUT USE DATABASE PRECISION YES
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layer pwell 41
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layer nwell 42
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layer active 43
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layer poly 46
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layer nimplant 45
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layer pimplant 44
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layer contact 25
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layer active_contact 48
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layer poly_contact 47
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layer metal1 49
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layer via1 50
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layer metal2 51
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layer via2 61
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layer metal3 62
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layer glass 52
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layer pad 26
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//Enabling incremental connectivity for antenna rule checks
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DRC Incremental Connect Yes
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well = nwell OR pwell
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gate = poly AND active
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implant = nimplant OR pimplant
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fieldpoly = poly NOT active
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contactenc1 = active OR poly
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contactenc = contactenc1 AND metal1
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diode = contact AND active
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act_poly = interact poly active
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GROUP mask_check
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//Well.2 Well.4
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Poly.1 Poly.2 Poly.3 Poly.4 Poly.5
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Active.1 Active.2 // Active.3
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Contact.1 Contact.2 Contact.3 Contact.4
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Contact.5 Contact.6 Metal1.1 Metal1.2 Metal1.3
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//Well.1 {
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//@Nwell and Pwell must not overlap
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//AND nwell pwell
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//}
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//Well.2 {
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//@Min spacing of pwell to nwell = 0.00
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//EXTERNAL nwell pwell < 0.00
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//}
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//Well.4 {
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//@Min width of nwell = 3.6
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//INTERNAL nwell < 3.6
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//}
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Poly.1 {
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@Min width of poly = 0.6
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INTERNAL poly < 0.6
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}
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Poly.2 {
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@Min spacing of gate poly = 0.9
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EXTERNAL gate < 0.9
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}
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Poly.3 {
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@Min extension of poly past active = 0.6
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ENCLOSURE active poly < 0.6
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}
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Poly.4 {
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@Minimum active enclosure of gate =0.6
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ENCLOSURE poly active < 0.6
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}
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Poly.5 {
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@Minimum spacing of poly to active = 0.3
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EXTERNAL act_poly active < 0.3
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}
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Active.1 {
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@Minimum width of active = 0.9
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INTERNAL active < 0.9
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}
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Active.2 {
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@Minimum spacing of active areas = 0.9
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EXTERNAL active < 0.9
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}
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//Active.3 {
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//@Minimum well enclosure of active = 1.8
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//ENCLOSURE active well < 1.8
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//}
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Contact.1 {
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@Minimum width of contact = 0.6
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INTERNAL contact < 0.6
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}
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Contact.2 {
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@Minimum spacing of contact = 0.9
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EXTERNAL contact < 0.9
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}
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Contact.3 {
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@Contact must be inside metal1 and active or poly
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NOT contact contactenc
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}
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Contact.4 {
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@Minimum active enclosure of contact = 0.3
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ENCLOSURE contact active < 0.3
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}
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Contact.5 {
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@Minimum poly enclosure of contact = 0.3
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ENCLOSURE contact poly < 0.3
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}
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Contact.6 {
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@Minimum spacing of contact to poly = 0.6
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EXTERNAL poly contact < 0.6
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}
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Metal1.1 {
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@Minimum width of metal1 = 0.9
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INTERNAL metal1 < 0.9
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}
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Metal1.2 {
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@Minimum spacing of metal1 = 0.9
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EXTERNAL metal1 < 0.9
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}
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Metal1.3 {
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@Metal1 must extend past contact by 0.3 on two opposite sides
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RECTANGLE ENCLOSURE contact metal1
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GOOD 0.00 0.3 OPPOSITE 0.00 0.3 OPPOSITE
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}
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Metal1.4 {
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@Metal1 must extend past via1 by 0.3 on two opposite sides
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RECTANGLE ENCLOSURE via1 metal1
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GOOD 0.00 0.3 OPPOSITE 0.00 0.3 OPPOSITE
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}
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Via1.1 {
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@Minimum width of via1 = 0.6
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INTERNAL via1 < 0.6
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}
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Via1.2 {
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@Minimum spacing of via1 = 0.6
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EXTERNAL via1 < 0.6
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}
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Via1.3 {
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@Via1 must be inside metal1
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NOT via1 metal1
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}
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Metal2.1 {
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@Minimum width of metal2 = 0.9
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INTERNAL metal2 < 0.9
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}
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Metal2.2 {
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@Minimum spacing of metal2 = 0.9
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EXTERNAL metal2 < 0.9
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}
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Metal2.3 {
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@Metal2 must extend past via1 by 0.3 on two opposite sides
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RECTANGLE ENCLOSURE via1 metal2
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GOOD 0.00 0.3 OPPOSITE 0.00 0.3 OPPOSITE
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}
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Metal2.4 {
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@Metal2 must extend past via2 by 0.3 on two opposite sides
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RECTANGLE ENCLOSURE via2 metal2
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GOOD 0.00 0.3 OPPOSITE 0.00 0.3 OPPOSITE
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}
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Via2.1 {
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@Minimum width of via2 = 0.6
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INTERNAL via2 < 0.6
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}
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Via2.2 {
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@Minimum spacing of via2 = 0.9
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EXTERNAL via2 < 0.9
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}
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Via2.3 {
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@Via2 must be inside metal2
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NOT via2 metal2
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}
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Via2.4 {
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@Via2 must be inside metal3
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NOT via2 metal3
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}
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Metal3.1 {
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@Minimum width of metal3 = 1.5
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INTERNAL metal3 < 1.5
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}
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Metal3.2 {
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@Minimum spacing of metal3 = 0.9
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EXTERNAL metal3 < 0.9
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}
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Metal3.3 {
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@Metal3 must extend past via2 by 0.6 on two opposite sides
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RECTANGLE ENCLOSURE via2 metal3
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GOOD 0.00 0.6 OPPOSITE 0.00 0.6 OPPOSITE
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}
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@ -0,0 +1,123 @@
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TITLE "LVS Rule File for scn3me_subm"
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LVS POWER NAME vdd
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LVS GROUND NAME gnd GROUND
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LVS REDUCE PARALLEL MOS yes
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LVS REDUCE SERIES MOS yes
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LVS REDUCE SEMI SERIES MOS yes
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LVS FILTER UNUSED MOS no
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LVS RECOGNIZE GATES all
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LVS COMPONENT TYPE PROPERTY element
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LVS COMPONENT SUBTYPE PROPERTY model
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LVS IGNORE PORTS no
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LVS REPORT mask.lvs.rep
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LVS REPORT OPTION N
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LVS REPORT MAXIMUM 50
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MASK RESULTS DATABASE maskdb
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precision 1000
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resolution 250
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TEXT LAYER metal1 metal2 metal3
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PORT LAYER TEXT metal1 metal2 metal3
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layer pwell 41
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layer nwell 42
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layer active 43
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layer poly 46
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layer nimplant 45
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layer pimplant 44
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layer contact 25
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layer active_contact 48
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layer poly_contact 47
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layer metal1 49
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layer via1 50
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layer metal2 51
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layer via2 61
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layer metal3 62
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layer glass 52
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layer pad 26
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connect metal1 metal2 by via1
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connect metal2 metal3 by via2
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pdif = active and pimplant // P-diffusion
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ndif = active and nimplant // N-diffusion
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ngate = poly and ndif // N-Transistor
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pgate = poly and pdif // P-transistor
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nsrcdrn = ndif not ngate // N-tansistor Source and Drain contacts diffusion region
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psrcdrn = pdif not pgate // P-tansistor Source and Drain contacts diffusion region
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pcont = psrcdrn and pwell
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ntapcont = active not interact pimplant
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ptapcont = active not interact nimplant
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bulk = extent
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nsub = (bulk not pwell) and nwell
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ncont = nsrcdrn and nsub
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connect metal1 poly psrcdrn nsrcdrn by contact mask
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connect psrcdrn pwell by pcont mask
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connect nsrcdrn nsub by ncont mask
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ncont1= ntapcont and nsub
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pcont1= ptapcont and pwell
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connect metal1 ncont1 by contact mask
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connect metal1 pcont1 by contact mask
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connect ncont1 nsub
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connect pcont1 pwell
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connect psrcdrn metal1 by contact
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connect nsrcdrn metal1 by contact
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connect psrcdrn metal1 by active_contact
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connect nsrcdrn metal1 by active_contact
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connect poly metal1 by contact
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connect poly metal1 by poly_contact
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device mp (p) pgate poly (G) psrcdrn (S) psrcdrn (D) nsub CMACRO FET_PROPERTIES pgate nsub
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device mn (n) ngate poly (G) nsrcdrn (S) nsrcdrn (D) pwell CMACRO FET_PROPERTIES ngate pwell
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VARIABLE trace_delta 4e-9
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DMACRO FET_TRACE device_type device_name {
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TRACE PROPERTY device_type(device_name) l l trace_delta ABSOLUTE
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TRACE PROPERTY device_type(device_name) w w trace_delta ABSOLUTE
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}
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CMACRO FET_TRACE MN n
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CMACRO FET_TRACE MP p
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DMACRO FET_PROPERTIES seed well{
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[
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PROPERTY W, L, AS, AD, PS, PD
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AS = area(S)
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AD = area(D)
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PS = perimeter(S)
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PD = perimeter(D)
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if ( AS == 0 ) {
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AD = area(D) / 2
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AS = AD
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PD = perimeter(D) / 2
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PS = PD
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}
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if ( AD == 0 ) {
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AS = area(S) / 2
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AD = AS
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PS = perimeter(S) / 2
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PD = PS
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}
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W = (perim_co(seed,S) + perim_co(seed,D) ) * 0.5
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L = (perim(seed) - perim_co(seed,S) - perim_in(seed,S) - perim_co(seed,D) - perim_in(seed,D) ) * 0.5
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]
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}
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