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OpenRAM
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131 Commits

Author SHA1 Message Date
Jesse Cirimelli-Low aedbc5f968 merge custom cell and module properties 2020-02-12 04:09:40 +00:00
Jesse Cirimelli-Low 18573c0e42 add module properties to other technologies 2020-02-05 22:25:35 +00:00
mrg 79391b84da Cleanup and rename vias. 2020-01-30 01:45:33 +00:00
Matt Guthaus 3147b99ce0 Merge remote-tracking branch 'bkoppelmann/bit-sym' into dev 2020-01-29 11:24:09 -08:00
Bastian Koppelmann df9f351a91 Add custom cell properties to technologies 
this is technology specific database to store data about the custom
design cells. For now it only contains on which axis the bitcells are
mirrored. This is a first step to support thin cells that need to be
mirrored on the x and y axis.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-01-28 15:46:14 +01:00
Bastian Koppelmann 407bd026ee tech: Make m3_stack the power_grid stack for FreePDK45/scn4m 
explicitly stating the power_grid makes people porting a new technology
aware of this option.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-01-28 12:06:38 +01:00
mrg 9beb0f4ece Add separate well design rules. 
Needed to fix various pgates with wells.
Did some cleanup of these gates as well.
 2020-01-23 19:43:41 +00:00
Matt Guthaus a8d370ee8c Improved comments in tech files 2019-12-20 16:35:31 -08:00
Matt Guthaus b7d78ec2ec Fix ptx active contact orientation to non-default M1 direction. 2019-12-19 12:54:10 -08:00
Matthew Guthaus 8e151553e4 Update contact types. 
Use preferred directions in tech files.
Programmatically generate based on interconnect stacks.
 2019-12-17 23:45:07 +00:00
Matt Guthaus 24546461ad Fix over-writing of active spacing rule. 2019-12-17 11:23:59 -08:00
Matt Guthaus ed28b4983b Clean up and generalize layer rules. 
Convert metalN to mN.
Generalize helper constants in modules for
space, width, enclose, etc.
Use layer stacks whever possible.
Try to remove drc() calls in liu of helper constants.
 2019-12-17 11:03:36 -08:00
Bastian Koppelmann 1380cbc50c technology: Add tech_module to all technologies 
this allows each technology to override each cell class.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2019-12-16 16:51:41 +01:00
Matt Guthaus 3ad7c8a8b5 Fix freepdk45 tech layer stacks 2019-12-13 14:25:00 -08:00
Matt Guthaus e048ada23c Abstract basic DRC checks 2019-12-11 17:56:55 -08:00
Matthew Guthaus d2cbc46527 Fix error 2019-12-06 00:05:26 +00:00
Matthew Guthaus 7397f110c5 Add bbox for special DRC rule boundary 2019-12-05 23:14:25 +00:00
Matt Guthaus 69bb245f28 Updates to gdsMill/tech layers 
Create active and poly contact types.
Define standard cell boundary option.
DataType and PurposeLayer are the same. Text must have type 0.
Remove vector from vlsiLayout. More debug in reader.
 2019-12-04 16:12:53 -08:00
Matt Guthaus 6ef1b6a4ec Blackbox option for DRC waivers 2019-11-29 15:50:32 -08:00
Matt Guthaus d511f648c6 Move DRC/LVS/PEX tools to tech file. 2019-11-29 12:01:33 -08:00
Matt Guthaus 102758881a Use layer instead of special flags for wells 2019-11-26 13:22:52 -08:00
Matthew Guthaus 131f4bda4a Add layer-purpose GDS support. Various PEP8 fixes. 2019-11-14 18:17:20 +00:00
Matt Guthaus ecbed870c0 Remove blockage layer. 2019-10-30 06:54:11 -07:00
Matt Guthaus 38213d998f Add separate layer and purpose pairs to tech layers. 2019-10-25 10:03:25 -07:00
Matt Guthaus 4c3b171b72 Share nominal temperature and voltage. Nominal instead of typical. 2019-09-04 16:53:58 -07:00
Matt Guthaus 585ce63dff Removing unused tech parms. Simplifying redundant parms. 2019-09-04 16:08:18 -07:00
Matt Guthaus c8c4d05bba Fix some regression fails. 2019-07-25 14:18:08 -07:00
Hunter Nichols 4e08e2da87 Merged and fixed conflicts with dev 2019-06-25 16:55:50 -07:00
Hunter Nichols 33c17ac41c Moved manual delay chain declarations from tech files to options. 2019-06-25 15:45:02 -07:00
Matt Guthaus a234b0af88 Fix space before comment 2019-06-14 08:43:41 -07:00
Matt Guthaus 0f03553689 Update copyright to correct years. 2019-05-06 06:50:15 -07:00
Matt Guthaus e071e53090 Add comments on gds units in tech files. 2019-04-30 10:13:13 -07:00
Matt Guthaus 3f9a987e51 Update copyright. Add header to all OpenRAM files. 2019-04-26 12:33:53 -07:00
Hunter Nichols 25c034f85d Added more accurate bitline delay capacitance estimations 2019-04-09 01:56:32 -07:00
Hunter Nichols edac60d2a8 Merged with dev and fixed conflicts. 2019-04-03 16:45:01 -07:00
Hunter Nichols cc5b347f42 Added analyical model test which compares measured delay to model delay. 2019-04-03 16:26:20 -07:00
Hunter Nichols f6eefc1728 Added updated analytical characterization with combined models 2019-04-02 01:09:31 -07:00
Matt Guthaus d178801882 Simplify tech organization and import 2019-03-06 07:41:38 -08:00
Hunter Nichols 0e96648211 Added linear corner factors in analytical delay model. 2019-03-04 00:42:18 -08:00
Hunter Nichols 8c1fe253d5 Added variable fanouts to delay testing. 2019-02-13 22:24:58 -08:00
Hunter Nichols 6d3884d60d Added corner data collection. 2019-01-22 16:40:46 -08:00
Hunter Nichols 8eb4812e16 Made parasitic delay parameter in Freepdk45 more accurate, added stage names to delay model. 2018-12-17 23:32:02 -08:00
Hunter Nichols 51b1bd46da Added option to use delay chain size defined in tech.py 2018-12-14 18:02:19 -08:00
Hunter Nichols 97fc37aec1 Added checks for the bitline voltage at sense amp enable 50%. 2018-12-12 23:59:32 -08:00
Hunter Nichols 8957c556db Added sense amp enable delay calculation. 2018-11-08 23:54:18 -08:00
Hunter Nichols b8061d3a4e Added initial code for determining the logical effort delay of the wordline. 2018-11-08 23:54:18 -08:00
Hunter Nichols 016604f846 Fixed spacing in golden lib files. Added column mux into analytical model. 2018-10-24 00:16:26 -07:00
Matt Guthaus 4bf1e206e2 Merge branch 'dev' into supply_routing 2018-10-17 09:47:18 -07:00
Michael Timothy Grimes e60deddfea adding 6T transistor size parameters to tech files for use in pbitcell. 2018-10-17 07:28:56 -07:00
Matt Guthaus 4932d83afc Add design rules classes for complex design rules 2018-10-12 09:44:36 -07:00
Matt Guthaus 823cb04b80 Fix metal4 rules in FreePDK45. Multiport still needs updating. 2018-10-11 09:56:15 -07:00
Matt Guthaus 1ed74cd571 Add minarea_metal4 in freepdk45 2018-10-10 15:33:16 -07:00
Hunter Nichols 5dfa8bc2c6 Fixed known typos of the word transition. 2018-09-10 14:27:26 -07:00
Matt Guthaus 378993ca22 Found rotate bug in transformCoordinate. Cleaned up transFlags. 2018-09-04 16:35:40 -07:00
Matt Guthaus e36452622c Preserve same order of design rules in each tech file 2018-08-29 16:12:06 -07:00
Michael Timothy Grimes 1f53a82d56 Fixed name for poly_to_polycontact rule. Previously said poly_to_contactpoly in error. 2018-08-29 15:04:17 -07:00
Michael Timothy Grimes 0182309f92 Editting comment on rule 5.5.b in scmos tech file. Adding complimentary rule to freepdk45 tech file. 2018-08-29 14:51:50 -07:00
Matt Guthaus 49bee6a96e Remove OEB signal since we split DIN/DOUT ports 2018-08-13 14:09:49 -07:00
Matt Guthaus 1f81b24e96 Single bank passing DRC and LVS again. 
Unfold hierarchical decoder to improve routability.
 2018-03-23 08:13:10 -07:00
Hunter Nichols e6d6680da1 Fixed conflict in delay.py 2018-02-27 13:02:22 -08:00
Hunter Nichols d0e6dc9ce7 First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level. 2018-02-26 16:32:28 -08:00
Matt Guthaus 9d1f31467e Move internal power to clock pin. Differentiate leakge power when CSb is high. 2018-02-23 12:21:32 -08:00
Hunter Nichols d4a0f48d4f Added power calculations for inverter. Still testing. 2018-02-21 19:51:21 -08:00
Matt Guthaus 0804a1eceb Add new DFF. Create DFF module. Start dff_array, not tested. 2018-02-14 15:16:28 -08:00
Matt Guthaus a12ebeed9f Add multiple process corners. Unit tests use nominal corner only. Add fake SCMOS nominal models, but they are broken. 2018-02-12 09:33:23 -08:00
Matt Guthaus f86985821a Begin modifications for corner-based characterization. Made stimuli.py a class. Golden output files are not updated. 2018-02-09 15:33:03 -08:00
Matt Guthaus efa465757c Remove dead code ptx_port. 2018-01-19 16:19:05 -08:00
Matt Guthaus 1701eac1a9 Added workaround to import layouts into Magic. Select and well layers in active contacts. Fixed missing implant enclose active DRC rule in parameterized cells. 2018-01-11 10:24:44 -08:00
Matt Guthaus e95988c639 Document tech files. Remove unused/redundant rules. Made rule names consistent/simple. 2018-01-08 11:57:51 -08:00
Matt Guthaus 8df46abb30 Move nmos gate to the top of the ptx. 2017-12-01 08:31:16 -08:00
Matt Guthaus 257cd62d25 Remove tools from tech file and have search order preference like spice. 2017-11-14 15:27:03 -08:00
Matt Guthaus 3e0f39cd8e Skeleton code for indirect DRC/LVS/PEX tools. 2017-11-14 14:59:14 -08:00
Matt Guthaus cf940fb15d Development version of new pin data structure. Tests pass LVS/DRC except for bank level. 2017-08-23 15:02:15 -07:00
Matt Guthaus 20d8c0bc45 Improved characterizer. 2017-07-06 08:42:25 -07:00
Matt Guthaus 34e180b901 Analytical delay model from Bin Wu. Unit test not passing. 2017-05-30 12:50:07 -07:00
mguthaus 7ca5c0b34f Added zoom to technology file so labels in each tech are readable size. Made default size. 2017-05-23 16:18:11 -07:00
Matt Guthaus fef708cffd Add slash in layers.map 2016-11-18 15:05:17 -08:00
Matt Guthaus 8934c1d3a4 Fixed layer map in runset files 2016-11-18 11:21:12 -08:00
Matt Guthaus b51c124810 Moved spice path to technology setup files instead of tech file itself. 2016-11-09 13:29:33 -08:00
Matt Guthaus db8a675d90 Clean up tech files to remove old parameters moved to premade cell classes. 2016-11-09 11:35:32 -08:00
Matt Guthaus f48272bde6 RELEASE 1.0 2016-11-08 09:57:35 -08:00