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OpenRAM
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2,514 Commits 4 Branches 63 Tags 78 MiB
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596 Commits

Author SHA1 Message Date
mrg 0837432d45 Wordline route layers and (optional) via. 2020-06-05 16:47:22 -07:00
mrg 5514996708 Auto-generate port dependent cell names. 2020-06-05 15:09:22 -07:00
mrg 00b51f5464 PEP8 format replica_bitcell_array 2020-06-05 13:49:32 -07:00
mrg 4fef632dce Fix syntax error 2020-06-05 12:13:41 -07:00
mrg a62b85a6b1 Update mirroring in port_data for bitcell mirrored arrays 2020-06-05 11:29:31 -07:00
mrg e14deff3d1 Fixed offset in port_data 2020-06-04 16:03:39 -07:00
mrg 2fcecb7227 Variable zjog. 512 port address test. s8 port address working. 2020-06-04 16:01:32 -07:00
mrg 7aafa43897 Connect RBL to bottom of precharge cell 2020-06-04 10:22:52 -07:00
mrg 249b5355ba Adjust rbl route 2020-06-03 17:08:04 -07:00
mrg 3927c62e32 Undo extra space due to nwell spacing 2020-06-03 16:39:33 -07:00
mrg 3b1fe26d25 Spacing between decoder and driver for s8 2020-06-03 14:33:30 -07:00
Joey Kunzler 6430aad857 Merge branch 'dev' into s8_update 2020-06-03 11:53:33 -07:00
mrg 34209dac3d A port option for correct mirroring in port_data. 2020-06-02 16:50:07 -07:00
Joey Kunzler 84021c9ccb merge conflict 2 - port data 2020-06-02 16:32:08 -07:00
Joey Kunzler 001bf1b827 merge conflict - port data 2020-06-02 14:15:39 -07:00
mrg fce8e878b9 Add port to col mux and simplify route with computation to fix mirror bug. 2020-06-02 13:57:41 -07:00
mrg fdf51c5a00 Add port option to precharge array 2020-06-02 11:44:22 -07:00
mrg f1b7b91b1a Use non-channel route for s8 port_data 2020-06-02 11:43:57 -07:00
mrg 45b0601e4b Fix via directions in s8 col mux 2020-06-02 11:43:31 -07:00
mrg a1c7474f80 Revert to channel route of bitlines 2020-06-02 10:08:53 -07:00
mrg b3b03d4d39 Hard cells can accept height parameter too. 2020-06-01 16:46:00 -07:00
mrg 496a24389c Remove prints 2020-05-29 16:57:47 -07:00
mrg 82dc937768 Add missing vias by using via stack function 2020-05-29 16:53:47 -07:00
Joey Kunzler b00163e4e1 lvs fix for regression tests 2020-05-29 13:50:34 -07:00
mrg 4a67f7dc71 Thin-cell decoder changes. 
Add hard decoder gates (nand, inv, pnan)
Add conditions for routing using LI layer in s8.
Generalize bus layers for decoders.
Move custom cells to own directory.
Fixed via directions, etc.
Add 4x16 hierarchical decoder and test case
 2020-05-29 10:36:07 -07:00
Joey Kunzler 218a553ac5 fix for replica column mirroring over y 2020-05-28 20:31:21 -07:00
Joey Kunzler 7505fa5aef update for end caps 2020-05-27 20:03:11 -07:00
Joey Kunzler 9a6b38b67e merge conflict 2020-05-26 16:03:36 -07:00
mrg 4b526f0d5f Check min size inverter. 2020-05-13 16:54:26 -07:00
mrg b7c66d7e07 Changes to simplify metal preferred directions and pitches. 
Changes to allow decoder height to be a 2x multiple of bitcell height.
Split of control logic tests.
Fixed track spacing in SRAM and channel router
PEP8 cleanup.
 2020-05-10 11:32:45 -07:00
mrg dd73afc983 Changes to allow decoder height to be a 2x multiple of bitcell height. 
Convert to use li layer in pgates.
Fix multifinger devices with li layers.
Simplify wordline driver input routing.
Fix power pin direction option update.
PEP8 cleanup
Changes to simplify metal preferred directions and pitches.
Split of control logic tests.
 2020-05-10 06:56:22 -07:00
Joey Kunzler 1b6634bb97 port data routing fix 2020-04-29 15:48:15 -07:00
Joey Kunzler 0bae652be9 fix merge conflicts 2020-04-23 11:51:46 -07:00
Joey Kunzler fed1c0bbe1 s8 col mux array 2020-04-22 16:22:34 -07:00
mrg 32576fb62c Convert wordline driver to pand2 rather than pnand2+pdriver 2020-04-22 13:27:50 -07:00
mrg f1c1adc9bd Simplify supply contacts in delay chain. 2020-04-21 16:12:54 -07:00
mrg 0f6998a1c5 PEP8 cleanup 2020-04-21 15:36:38 -07:00
mrg cd66ddb37c Add supply rails to dff array. PEP8 cleanup. 2020-04-21 15:21:29 -07:00
mrg f6135f3471 PEP8 formatting 2020-04-20 16:38:30 -07:00
mrg 7995451cbb PEP8 formatting 2020-04-20 14:45:18 -07:00
mrg 7f65176908 Configured bitline directions into prot_data 2020-04-20 14:23:40 -07:00
mrg 843e9414df Parameterize vdd and gnd pin in write driver array. 2020-04-16 11:28:35 -07:00
mrg 770533e7b1 Parameterize vdd and gnd pin in sense amp array. 2020-04-16 11:27:26 -07:00
mrg 9d2902de9e Conditional well spacing 2020-04-15 15:55:49 -07:00
mrg e95c97d7a5 PEP8 cleanup 2020-04-15 14:29:43 -07:00
mrg 331a4f4606 Fix wire width bug in short jogs. PEP8 cleanup. 2020-04-15 09:48:42 -07:00
mrg 0941ebc3da Fix well spacing issue 2020-04-14 14:08:07 -07:00
mrg 32d190b8b1 Jog connection on M1 for bank select. 2020-04-14 12:15:56 -07:00
mrg 43dcf675a1 Move pnand outputs to M1. Debug hierarchical decoder multirow. 2020-04-14 10:52:25 -07:00
mrg 2e67d44cd7 First pass of multiple bitcells per decoder row 2020-04-10 13:29:41 -07:00