..
bank.py
Move rbl route away from bitcell array
2020-03-06 09:48:20 -08:00
bank_select.py
Fix well spacing issue
2020-04-14 14:08:07 -07:00
bitcell_array.py
Configured bitline directions into prot_data
2020-04-20 14:23:40 -07:00
bitcell_base_array.py
Changes to allow decoder height to be a 2x multiple of bitcell height.
2020-05-10 06:56:22 -07:00
control_logic.py
Convert wordline driver to pand2 rather than pnand2+pdriver
2020-04-22 13:27:50 -07:00
delay_chain.py
Changes to allow decoder height to be a 2x multiple of bitcell height.
2020-05-10 06:56:22 -07:00
dff.py
merge custom cell and module properties
2020-02-12 04:09:40 +00:00
dff_array.py
add custom module file, make dff clk pin dynamic
2020-02-04 23:35:06 -08:00
dff_buf.py
Add supply rails to dff array. PEP8 cleanup.
2020-04-21 15:21:29 -07:00
dff_buf_array.py
Add supply rails to dff array. PEP8 cleanup.
2020-04-21 15:21:29 -07:00
dff_inv.py
Clean up and generalize layer rules.
2019-12-17 11:03:36 -08:00
dff_inv_array.py
Clean up and generalize layer rules.
2019-12-17 11:03:36 -08:00
dummy_array.py
Fix base bitcell syntax error. Remove some unused imports.
2020-01-30 01:58:30 +00:00
hierarchical_decoder.py
Changes to allow decoder height to be a 2x multiple of bitcell height.
2020-05-10 06:56:22 -07:00
hierarchical_predecode.py
Changes to allow decoder height to be a 2x multiple of bitcell height.
2020-05-10 06:56:22 -07:00
hierarchical_predecode2x4.py
Convert pnand+pinv to pand in decoders.
2020-03-06 13:26:40 -08:00
hierarchical_predecode3x8.py
Convert pnand+pinv to pand in decoders.
2020-03-06 13:26:40 -08:00
module_type.py
Cleanup and rename vias.
2020-01-30 01:45:33 +00:00
multibank.py
Cleanup and rename vias.
2020-01-30 01:45:33 +00:00
port_address.py
Change rows to outputs in hierarchical decoder
2020-04-08 17:05:16 -07:00
port_data.py
Configured bitline directions into prot_data
2020-04-20 14:23:40 -07:00
precharge_array.py
Add licon option to precharge
2020-04-01 11:26:45 -07:00
replica_bitcell_array.py
replica_bitcell_array: Connect bitcells based on bitcell bl/br/wl names
2020-02-12 15:37:47 +01:00
replica_column.py
Bitcell arrays: Allow mirroring on the y axis
2020-01-28 15:51:21 +01:00
sense_amp.py
sense_amp: Allow custom pin names
2020-02-17 15:20:12 +01:00
sense_amp_array.py
Parameterize vdd and gnd pin in sense amp array.
2020-04-16 11:27:26 -07:00
single_level_column_mux_array.py
fix merge conflicts
2020-04-23 11:51:46 -07:00
tri_gate.py
Made all cin function relate to farads and all input_load relate to relative units.
2019-08-08 01:57:04 -07:00
tri_gate_array.py
Clean up and generalize layer rules.
2019-12-17 11:03:36 -08:00
wordline_driver.py
Changes to allow decoder height to be a 2x multiple of bitcell height.
2020-05-10 06:56:22 -07:00
write_driver.py
write_driver: Allow custom pin names
2020-02-17 14:25:00 +01:00
write_driver_array.py
Parameterize vdd and gnd pin in write driver array.
2020-04-16 11:28:35 -07:00
write_mask_and_array.py
Move write mask vias to center to avoid data pins.
2019-12-20 11:48:27 -08:00
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