luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
4,127 Commits 4 Branches 63 Tags 78 MiB
Commit Graph

73 Commits

Author SHA1 Message Date
mrg d92c7a634d Use packages for imports. 
Must set PYTHONPATH to include OPENRAM_HOME now.
Reorganizes subdirs as packages.
Rewrites unit tests to use packages.
Update README.md with instructions, dependencies etc.
Update sky130 module imports.
Change tech specific package from modules to custom.
 2022-07-13 15:55:57 -07:00
mrg 357f967a93 Leave supply routing to new helper functions. 2022-05-11 11:01:14 -07:00
mrg d69e55c2e3 Power routing changes. 
Make the power rails an "experimental_power" option and conditional.
Rename route_vdd_gnd to route_supplies everywhere for consistency.
 2022-03-06 09:56:00 -08:00
mrg f7e3672c89 Route horizontal supplies in write driver. 2022-03-01 14:37:51 -08:00
mrg baf369fc96 Convert power to rails rather than pins in sense amp and precharge 2022-02-23 14:06:49 -08:00
mrg 0c3ee643ab Remove add_mod and add module whenever calling add_inst. 2021-11-22 11:33:27 -08:00
Jesse Cirimelli-Low 6d8411d19f use consistent amp spacing 2021-05-07 11:29:43 -07:00
Jesse Cirimelli-Low 3a3da9e0d7 56 drc errors on col mux 1port 2021-05-02 21:49:09 -07:00
mrg 1c6de4591d Remove vertical power pin vias. 2021-02-23 13:32:00 -08:00
Matt Guthaus 30fc81a1f0 Update copyright year. 2021-01-22 11:23:28 -08:00
mrg 01d312d65c Refactor add power pins 2021-01-13 10:57:12 -08:00
mrg 8021430122 Fix pbitcell erros 2020-11-13 15:55:55 -08:00
mrg 8be1436d51 Use OPTS.bitcell everywhere 2020-11-05 16:55:08 -08:00
mrg da721a677d Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
mrg c12720a93f Extend pin correct length in new array. 2020-09-14 12:53:59 -07:00
mrg e95ab66916 Update to space according to the bitcell array. 2020-09-14 12:05:45 -07:00
mrg 8909ad7165 Update modules to use variable bit offsets. 
Bitcell arrays can return the bit offsets.
Port data and submodules can use offsets for spacing.
Default spacing for port data if no offsets given.
 2020-09-11 15:36:22 -07:00
Hunter Nichols 73b2277daa Removed dead code related to older characterization scheme 2020-08-27 17:30:58 -07:00
mrg 30976df48f Change inheritance inits to use super 2020-08-06 11:33:26 -07:00
mrg 459e3789b8 Change control layers in sky130. 2020-06-29 16:23:25 -07:00
mrg f57eeb88eb PEP8 cleanup, multiple vdd/gnd support 2020-06-26 11:47:55 -07:00
Aditi Sinha d5041afebc Merge branch 'dev' into bisr 2020-06-07 16:27:25 +00:00
mrg a62b85a6b1 Update mirroring in port_data for bitcell mirrored arrays 2020-06-05 11:29:31 -07:00
Aditi Sinha a5c211bd90 Merge branch 'dev' into bisr 2020-05-13 22:39:29 +00:00
mrg b7c66d7e07 Changes to simplify metal preferred directions and pitches. 
Changes to allow decoder height to be a 2x multiple of bitcell height.
Split of control logic tests.
Fixed track spacing in SRAM and channel router
PEP8 cleanup.
 2020-05-10 11:32:45 -07:00
Aditi Sinha 2498ff07ea Merge branch 'dev' into bisr 2020-05-02 07:48:35 +00:00
mrg 770533e7b1 Parameterize vdd and gnd pin in sense amp array. 2020-04-16 11:27:26 -07:00
Aditi Sinha 2661a42726 changes to support spare columns 2020-04-14 03:09:10 +00:00
mrg d916322b74 PEP8 updates 2020-03-31 10:15:46 -07:00
Joey Kunzler b0d2946c80 update to sense amp and write driver modules 2020-03-30 20:00:32 -07:00
Bastian Koppelmann 76256a2f1b sense_amp: Allow custom pin names 
we don't want to propagate the sense amp's bl/br names out of the
sense_amp_array. Thus the sense_amp_array gets them named as
"bl"/"br" again.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-02-17 15:20:12 +01:00
Bastian Koppelmann 680dc6d2c7 sense_amp/array: Remove hardcoded pin names 
all pin names should be wrapped into a function/property. This ensures
that there is exactly one place to change the name.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-02-17 15:20:06 +01:00
Bastian Koppelmann 5e1f64c8f9 modules/port_data: Add get_bl/br_name method 
if we rely on the names of the submodules (sense_amp_array,
write_driver_array, etc.) for port_data's pins, we get into trouble on
multiport SRAMs. To avoid this we use explicit names for br/bl depending
on the port number in port_data. Now each submodule does no longer need to
figure out the right name depending on the port number.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-02-17 14:18:32 +01:00
Bastian Koppelmann f9babcf666 port_data: Each submodule now specifies their bl/br names 
before the names of bl/br from the bitcell were assumed. If we want to
allow renaming of bl/br from bitcells, we have to seperate the other
modules from that. Note, that we don't touch every occurence of bl/br,
but only the once necessary that pin renaming of the bitcell works.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-02-12 15:00:50 +01:00
Matt Guthaus 3147b99ce0 Merge remote-tracking branch 'bkoppelmann/bit-sym' into dev 2020-01-29 11:24:09 -08:00
Bastian Koppelmann ed66fca031 write_driver/sense_amp/precharge arrays: Allow y axis mirroring 
since the bitlines alternate in the bitcell array we also need to mirror
the port_data elements.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-01-28 15:51:39 +01:00
Bastian Koppelmann 90a4a72bba modules: Use add_power_pin API for all modules 
sense_amp_array, write_driver_array, and single_column_mux were the only offenders.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-01-28 11:47:49 +01:00
Matt Guthaus ed28b4983b Clean up and generalize layer rules. 
Convert metalN to mN.
Generalize helper constants in modules for
space, width, enclose, etc.
Use layer stacks whever possible.
Try to remove drc() calls in liu of helper constants.
 2019-12-17 11:03:36 -08:00
Matt Guthaus e143a6033f Use layer stacks from tech file in design class and throughout 2019-12-13 14:13:41 -08:00
Hunter Nichols 3c44ce2df6 Replaced analytical characterization with graph implementation. Removed most analytical delay functions used by old chacterizer. 2019-08-08 02:33:51 -07:00
Matt Guthaus ad35f8745e Add direction to pins of all modules 2019-08-06 14:14:09 -07:00
Matt Guthaus 6e044b776f Merge branch 'pep8_cleanup' into dev 2019-06-14 08:47:10 -07:00
Matt Guthaus a234b0af88 Fix space before comment 2019-06-14 08:43:41 -07:00
mrg fc12ea24e9 Add boundary to every module and pgate for visual debug. 2019-06-03 15:27:37 -07:00
Matt Guthaus 0f03553689 Update copyright to correct years. 2019-05-06 06:50:15 -07:00
Matt Guthaus 3f9a987e51 Update copyright. Add header to all OpenRAM files. 2019-04-26 12:33:53 -07:00
Hunter Nichols 25c034f85d Added more accurate bitline delay capacitance estimations 2019-04-09 01:56:32 -07:00
Hunter Nichols cc5b347f42 Added analyical model test which compares measured delay to model delay. 2019-04-03 16:26:20 -07:00
Hunter Nichols f6eefc1728 Added updated analytical characterization with combined models 2019-04-02 01:09:31 -07:00
Hunter Nichols 0e96648211 Added linear corner factors in analytical delay model. 2019-03-04 00:42:18 -08:00