2256 Commits

Author	SHA1	Message	Date
mrg	031862c749	Add metal enclosure to base case of center via stack.	2020-06-23 11:56:50 -07:00
mrg	1a528f9739	Skip and4_dec test	2020-06-23 10:08:28 -07:00
mrg	7ea3366ef1	Disable magic filter in sky130	2020-06-22 16:58:01 -07:00
mrg	92fc30005c	Use factory in and_dec tests	2020-06-22 16:55:49 -07:00
mrg	40edbfa51f	Error out on single port in sky130	2020-06-22 15:41:59 -07:00
mrg	cd23b31ab4	Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev	2020-06-22 12:55:45 -07:00
mrg	0926eab9f5	PEP8 formatting	2020-06-22 12:55:18 -07:00
mrg	54120f8405	Add option for removing subckt/instances of cells for row/col caps	2020-06-22 12:35:37 -07:00
mrg	a13d535945	PEP8 cleanup	2020-06-22 11:33:02 -07:00
Joey Kunzler	8166adc512	Merge branch 'dev' into s8_update	2020-06-19 15:35:49 -07:00
Joey Kunzler	208c652653	added error for sky130 with invalid x mirroring (for lvs)	2020-06-19 13:59:33 -07:00
mrg	a2d160dbf5	Copy magic config for filter code	2020-06-19 13:40:45 -07:00
mrg	5872f553e1	Rename tests for consistency	2020-06-19 08:53:35 -07:00
mrg	239b3ea007	Make wmask test a 1rw/1r	2020-06-19 08:49:48 -07:00
mrg	617a84d4b8	Fix output name of magic gds filter	2020-06-19 07:15:27 -07:00
mrg	94c480911b	ngspice raw save doesn't work with measures	2020-06-19 07:09:15 -07:00
mrg	231f90f492	Fix missing space in ptx spice line	2020-06-19 06:47:46 -07:00
mrg	403ea17039	PEP8 formatting	2020-06-18 14:55:01 -07:00
mrg	69f5621245	Save raw file from ngspice	2020-06-18 14:54:36 -07:00
mrg	7dfc462ef6	Add magic filter before calibre for sky130	2020-06-15 13:58:26 -07:00
mrg	abb5ff7bae	Separate route conditions for s8	2020-06-15 10:30:27 -07:00
mrg	e331d6fae8	Permute bus order to avoid conflict in control_logic	2020-06-15 10:25:53 -07:00
mrg	a862cf3cb2	Test more single level col mux configs	2020-06-15 10:17:54 -07:00
mrg	4cb827c3d7	Add redundant implant for s8	2020-06-15 10:08:07 -07:00
mrg	355474ce2c	Playing around with pnand2 pin spacing rules	2020-06-15 10:07:00 -07:00
mrg	6e0008403e	Update new tech name	2020-06-15 10:06:17 -07:00
mrg	79b3b9a8b0	Switch input/output layers for predecodes	2020-06-15 10:06:04 -07:00
mrg	6c04166876	Update port data wmask tests	2020-06-15 06:05:05 -07:00
mrg	02352c35d7	Fix hard coded layer in wmask	2020-06-14 17:10:32 -07:00
mrg	52ee7b0a19	Disable perimeter pins and make an option	2020-06-14 16:44:10 -07:00
mrg	78be9f367a	Add brain-dead router pins to perimeter	2020-06-14 15:52:09 -07:00
mrg	9930b5f3f6	Do not run tapless unit tests	2020-06-14 14:18:25 -07:00
mrg	7dc33285a7	Add contact to gate design rule to max for spacing inputs	2020-06-14 14:18:08 -07:00
mrg	8e8a97cc4b	Add correct boundary to SRAM	2020-06-14 14:17:35 -07:00
mrg	443c401561	pnand2 B input spaced from top	2020-06-14 14:17:04 -07:00
mrg	91f20f2cf6	Better centering of pinv_dec	2020-06-14 14:09:45 -07:00
mrg	8f1dc7eeea	Include mirror/rotate on translate_all boundary update	2020-06-13 06:50:53 -07:00
mrg	33a32101c9	DRC and LVS fixes for pinv_dec	2020-06-12 15:23:51 -07:00
mrg	443b8fbe23	Change s8 to sky130	2020-06-12 14:23:26 -07:00
mrg	54e4d147f6	Rail to ptx spacing based on routing layer not m1	2020-06-11 15:03:50 -07:00
mrg	e9780ea599	Add non-preferred directions for channel routes	2020-06-11 15:03:36 -07:00
mrg	8d52794c32	Remove printf in precharge	2020-06-11 11:57:52 -07:00
mrg	7ad2d54a69	Add pin and label purposes	2020-06-11 11:54:51 -07:00
mrg	1a2e0046b1	Add contact to gate spacing for precharge	2020-06-11 11:54:34 -07:00
mrg	089331ced3	Add stdc bounding box too	2020-06-11 11:54:16 -07:00
mrg	098219d56c	Add npc enclosure to poly contacts	2020-06-11 11:53:59 -07:00
mrg	f973dd6a5c	Save LVS model with no u too for Calibre	2020-06-11 11:53:34 -07:00
mrg	dff28a9997	Merge branch 'tech_migration' into dev	2020-06-10 17:09:05 -07:00
mrg	196e5998c8	Half poly space per cell at top and bottom.	2020-06-10 16:52:51 -07:00
mrg	fdf92d0da1	Rename test 14	2020-06-10 16:41:26 -07:00