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5497 Commits

Author SHA1 Message Date
AdvaySingh1 8536ab69c1 Added -o option for output file in struct_partition 2026-03-19 10:09:11 -07:00
AdvaySingh1 52fad78b40 Removed is_port for non-trigger outputs. TODO: add a flag which does this so POs are only those ones 2026-03-19 09:23:12 -07:00
AdvaySingh1 dc73249d8f Added support for printing the signal map 2026-03-18 16:23:41 -07:00
AdvaySingh1 a3ffc5da30 Added new passes/sat/struct_partition.cc pass to propagate the ports out 2026-03-18 11:53:47 -07:00
Akash Levy a67471d7f9
Merge pull request #115 from Silimate/sat_clkgate 
Sat clkgate
 2026-03-04 18:02:27 -08:00
AdvaySingh1 e2b71b0d55 Added -word arg 2026-03-04 14:51:47 -08:00
AdvaySingh1 26adc17fd7 Revert "Changed to for chacterization" 
Removing changing _DFF_ to dff for chacterization
 2026-03-04 10:43:53 -08:00
Akash Levy d05236907a Merge branch 'main' into sim 2026-03-03 20:58:07 -08:00
Akash Levy 96104b4431 Merge branch 'main' into sat_clkgate 2026-03-03 20:57:42 -08:00
Akash Levy 958f1c608a
Merge pull request #116 from Silimate/autoscope 
Autoscope
 2026-03-03 20:49:13 -08:00
tondapusili b438fd1fe9 negopt: fix quadratic blowup by adding index hints and deferring nusers to filter 2026-03-02 19:33:25 -08:00
Stan Lee da25b800bc finalized 2026-03-02 11:05:44 -08:00
Akash Levy 7d96a7f73c Update aigmap to go a lot faster using aig template cache and uniquify cache 2026-03-01 22:35:06 -08:00
Akash Levy b03f73653f Update abc to fix bug 2026-03-01 21:43:26 -08:00
Stan Lee c459a74c13 autoscoping 2026-03-01 15:39:35 -08:00
Akash Levy 7a35a982d3
Merge pull request #111 from Silimate/timing_balance_impl 
silimate: add opt_timing_balance pass and tests
 2026-02-28 12:22:23 -08:00
AdvaySingh1 877e97de06 Changed to for chacterization 2026-02-27 15:23:50 -08:00
Advay Singh 8974f3473f
Update passes/silimate/infer_ce.cc 
Co-authored-by: greptile-apps[bot] <165735046+greptile-apps[bot]@users.noreply.github.com>
 2026-02-27 12:37:49 -08:00
AdvaySingh1 90aa1cc016 Checked out main passes/techmap/clockgate.cc for source attributes and removed logging 2026-02-27 12:24:31 -08:00
AdvaySingh1 3cee420bf9 Merge branch 'main' into sat_clkgate 2026-02-27 11:15:22 -08:00
tondapusili f46b8d2a44 silimate: add opt_timing_balance pass and tests 2026-02-27 09:13:39 -08:00
Stan Lee 29a1c69f74 move log flush to better spot 2026-02-26 16:01:37 -08:00
Stan Lee b11eef4fe1 fix bug 2026-02-26 16:00:27 -08:00
tondapusili 2f276d0723 Added log flushes after each negopt pass for clearer logging 2026-02-25 12:15:46 -08:00
Akash Levy 0b46d8b201
Merge pull request #109 from Silimate/clkgate_attr 
Added is_clock_gated attr to flops created via clockgate.cc pass
 2026-02-20 17:02:02 -08:00
AdvaySingh1 ec537b189f Added is_clock_gated attr to flops created via clockgate.cc pass 2026-02-20 11:34:50 -08:00
AdvaySingh1 8f5b8cb46c Added is_clock_gated attr to flops created via clockgate.cc pass 2026-02-20 11:34:08 -08:00
AdvaySingh1 84a03a6b9a Merge branch 'icg_builtin_sim' into sat_clkgate 2026-02-19 11:51:49 -08:00
AdvaySingh1 b29514fafc Added built in cell alongside sim support for cell 2026-02-19 11:48:35 -08:00
AdvaySingh1 d9867fc7c7 Merge branch 'main' into sat_clkgate 2026-02-19 09:43:22 -08:00
AdvaySingh1 5e58bf22e0 Changed param naming for consistancy 2026-02-19 09:42:59 -08:00
Akash Levy 723ddd74cf Improve wreduce runtime 2026-02-19 01:03:26 -08:00
AdvaySingh1 5769cdbea8 Added node retention 2026-02-18 16:05:56 -08:00
AdvaySingh1 d84e56ecac Added naming for the new icg cells 2026-02-18 16:03:34 -08:00
AdvaySingh1 ee896b9eee Removed sorting of similar candidate_gates for unnessessary optimization 2026-02-18 09:08:25 -08:00
Akash Levy c04975b78c Remove custom mux opt_exprs 2026-02-17 20:41:29 -08:00
AdvaySingh1 6cb9fadded Removed downstream signals causing equiv_opt failures due to feedback loop 2026-02-17 16:22:59 -08:00
AdvaySingh1 90dbb91cae Changed min cone size 2026-02-17 16:22:05 -08:00
AdvaySingh1 2ab89e1146 Passing equiv_opt pass and speed boosts 2026-02-17 16:13:51 -08:00
AdvaySingh1 c8b6869e65 Removed optimizations from infer_ce.cc for profiling 2026-02-17 15:20:57 -08:00
AdvaySingh1 a8e4fccc56 Removed simulation and isValidGatingSignal function 2026-02-17 14:07:22 -08:00
AdvaySingh1 fa9e7a77d7 Removed normal clockgate pass options form sate_clockgate pass 2026-02-17 13:43:22 -08:00
AdvaySingh1 efcabb270f Added caching of simulation runs for speed 2026-02-17 13:38:32 -08:00
AdvaySingh1 499e83a549 Switched to using CE module. Mostly retaining SAT gates. Still needs speedup 2026-02-17 12:41:59 -08:00
AdvaySingh1 e755f6c42e Added initial simulation. Incorrect simulation -- changed the number of accedpted results as well as increasing runtime 2026-02-17 12:14:53 -08:00
AdvaySingh1 2212d85626 Changed configurations to match the OpenROAD project 2026-02-17 11:57:56 -08:00
AdvaySingh1 144db54c4e Changed to inverse hashing for more flexibility 2026-02-17 11:53:06 -08:00
AdvaySingh1 f0de3ae8de Initial sat_clockgate pass pre speed optimization 2026-02-17 11:19:18 -08:00
AdvaySingh1 cc6605f8e2 Added passing on the args into the clockgate pass so there's an icg cell for the mapping 2026-02-17 10:49:18 -08:00
AdvaySingh1 2ab34262ec Added profiling info before and after sat_clockgate pass 2026-02-17 09:23:32 -08:00