luke
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Checked out main passes/techmap/clockgate.cc for source attributes and removed logging

This commit is contained in:
AdvaySingh1 2026-02-27 12:24:31 -08:00
parent ce95d7cbcf
commit 90aa1cc016
1 changed files with 0 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
passes/techmap/clockgate.cc
View File

@ -341,8 +341,6 @@ struct ClockgatePass : public Pass {
pool<Cell*> ce_ffs;
dict<ClkNetInfo, GClkNetInfo> clk_nets;
log("Found %zu CE FFs\n", ce_ffs.size());
int gated_flop_count = 0;
for (auto module : design->selected_unboxed_whole_modules()) {
for (auto cell : module->cells()) {
@ -352,14 +350,11 @@ struct ClockgatePass : public Pass {
FfData ff(nullptr, cell);
// It would be odd to get constants, but we better handle it
if (ff.has_ce) {
log("FF %s has CE\n", cell->name);
if (!ff.sig_clk.is_bit() || !ff.sig_ce.is_bit())
continue;
if (!ff.sig_clk[0].is_wire() || !ff.sig_ce[0].is_wire())
continue;
log("FF %s has valid CE and CLK\n", cell->name);
ce_ffs.insert(cell);
ClkNetInfo info = clk_info_from_ff(ff);
@ -370,8 +365,6 @@ struct ClockgatePass : public Pass {
}
}
log("Found %zu clk_nets\n", clk_nets.size());
for (auto& clk_net : clk_nets) {
auto& clk = clk_net.first;
auto& gclk = clk_net.second;
@ -410,15 +403,12 @@ struct ClockgatePass : public Pass {
}
}
log("Found %zu clk_nets\n", clk_nets.size());
for (auto cell : ce_ffs) {
FfData ff(nullptr, cell);
ClkNetInfo info = clk_info_from_ff(ff);
auto it = clk_nets.find(info);
log_assert(it != clk_nets.end() && "Bug: desync ce_ffs and clk_nets");
log("Found new_net for %s\n", cell->name);
if (!it->second.new_net)
continue;
@ -430,16 +420,6 @@ struct ClockgatePass : public Pass {
it->second.src_count++;
}
// Accumulate src attributes from all FFs sharing this ICG
if (max_src < 0 || it->second.src_count < max_src) {
it->second.icg_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
if (it->second.ce_not_cell)
it->second.ce_not_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
it->second.src_count++;
}
log("Tryuing to fix up FF %s\n", cell->name);
log_debug("Fix up FF %s\n", cell->name);
// Now we start messing with the design
ff.has_ce = false;