luke
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Changed to for chacterization

This commit is contained in:
AdvaySingh1 2026-02-27 15:23:50 -08:00
parent 8974f3473f
commit 877e97de06
1 changed files with 6 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
passes/techmap/clockgate.cc
View File

@ -395,9 +395,12 @@ struct ClockgatePass : public Pass {
// Fix CE polarity if needed
if (!clk.pol_ce) {
Wire *ce_not_wire = module->addWire(NEW_ID2_SUFFIX("ce_not_w"));
Cell *ce_not = module->addCell(NEW_ID2_SUFFIX("ce_not"), ID($_NOT_));
ce_not->setPort(ID::A, clk.ce_bit);
ce_not->setPort(ID::Y, ce_not_wire);
Cell *ce_not = module->addCell(NEW_ID2_SUFFIX("ce_not"), ID($not));
ce_not->setParam(ID::A_SIGNED, 0);
ce_not->setParam(ID::A_WIDTH, 1);
ce_not->setParam(ID::Y_WIDTH, 1);
ce_not->setPort(ID::A, clk.ce_bit);
ce_not->setPort(ID::Y, ce_not_wire);
gclk.ce_not_cell = ce_not;
icg->setPort(matching_icg_desc->ce_pin, ce_not_wire);
}