mirror of https://github.com/YosysHQ/yosys.git
Improve wreduce runtime
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bf4ce9d6f7
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723ddd74cf
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@ -462,7 +462,7 @@ struct WreduceWorker
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return count;
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}
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void run_wire(Wire *w, pool<SigSpec> complete_wires)
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void run_wire(Wire *w, const pool<SigSpec> &complete_wires)
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{
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int unused_top_bits = 0;
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@ -482,7 +482,7 @@ struct WreduceWorker
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if (unused_top_bits == 0 || unused_top_bits == GetSize(w))
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return;
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if (complete_wires[mi.sigmap(w).extract(0, GetSize(w) - unused_top_bits)])
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if (complete_wires.count(mi.sigmap(w).extract(0, GetSize(w) - unused_top_bits)))
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return;
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log_debug("Removed top %d bits (of %d) from wire %s.%s.\n", unused_top_bits, GetSize(w), log_id(module), log_id(w));
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@ -512,21 +512,25 @@ struct WreduceWorker
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keep_bits.insert(bit);
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}
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while (!work_queue_cells.empty() && !work_queue_wires.empty())
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while (!work_queue_cells.empty() || !work_queue_wires.empty())
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{
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// Initialize complete wires
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pool<SigSpec> complete_wires;
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for (auto w : module->wires())
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complete_wires.insert(mi.sigmap(w));
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// Run cells
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work_queue_bits.clear();
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for (auto c : work_queue_cells)
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run_cell(c);
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// Run wires
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for (auto w : work_queue_wires)
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run_wire(w, complete_wires);
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if (!work_queue_wires.empty()) {
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pool<SigSpec> complete_wires;
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for (auto w : module->wires())
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complete_wires.insert(mi.sigmap(w));
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for (auto w : work_queue_wires)
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run_wire(w, complete_wires);
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}
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// Skip reload if nothing changed
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if (work_queue_bits.empty())
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break;
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// Get next batch of cells to process
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work_queue_cells.clear();
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@ -541,8 +545,9 @@ struct WreduceWorker
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if (bit.wire != NULL && module->selected(bit.wire))
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work_queue_wires.insert(bit.wire);
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// Reload module
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mi.reload_module();
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// Reload module only if there is more work to do
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if (!work_queue_cells.empty() || !work_queue_wires.empty())
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mi.reload_module();
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}
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}
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};
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