5609 Commits

Author	SHA1	Message	Date
Akash Levy	1cc35aa76d	Merge pull request #162 from Silimate/feat/chunk-parallel-sim ... [ENG-1969] Resim each instance independently	2026-05-12 01:29:47 -07:00
Chia-Hsiang Chang	67373542ae	fix: add guard to avoid crash on null-pointer dereference	2026-05-12 00:32:45 -07:00
Chia-Hsiang Chang	0dcfe5cd4b	chore: add comments and log	2026-05-12 00:21:25 -07:00
Chia-Hsiang Chang	eb83c40d24	fix: check the cell is a child node before skipping	2026-05-12 00:07:00 -07:00
Chia-Hsiang Chang	9e6d66d74e	chore: log error when no scope found	2026-05-12 00:01:29 -07:00
Stan Lee	7537faa8cd	add warning and calculate correct activity	2026-05-11 22:27:33 -07:00
Stan Lee	74dee77d9d	rm sigmap	2026-05-11 18:42:57 -07:00
Stan Lee	517a174775	Update passes/techmap/clockgate.cc ... Co-authored-by: greptile-apps[bot] <165735046+greptile-apps[bot]@users.noreply.github.com>	2026-05-11 18:41:18 -07:00
Chia-Hsiang Chang	a00bb2b80b	fix: don't recursively update children	2026-05-11 18:09:06 -07:00
Chia-Hsiang Chang	7b2e63ac5b	refactor: style fix	2026-05-11 16:09:02 -07:00
Stan Lee	1be9a8985d	bug fixes	2026-05-11 16:01:39 -07:00
Stan Lee	1b89bc7675	activity based clock gating	2026-05-11 10:55:53 -07:00
Chia-Hsiang Chang	57c3e484e3	feat: parallel resim with chunks and bb	2026-05-08 18:54:18 -07:00
Chia-Hsiang Chang	a3d81a6d3f	refactor	2026-05-06 18:27:57 -07:00
Chia-Hsiang Chang	8a5a7c6fe6	feat: each instance simulates independently	2026-05-06 17:26:42 -07:00
Akash Levy	b9fa4f85ba	Ignore DW in opt_hier/opt_boundary	2026-05-04 12:52:47 -07:00
Akash Levy	ebf269bdf0	opt_boundary improvements and add to opt pass as option	2026-05-04 10:51:04 -07:00
Akash Levy	4b219f0ef6	Improvements	2026-05-01 22:50:43 -07:00
Akash Levy	7db8f29c04	opt_boundary	2026-05-01 19:57:00 -07:00
Stan Lee	386d3fc308	fix	2026-04-30 12:30:09 -07:00
Stan Lee	9d9ed4bfe3	flatten VCD/RTL scope hierarchy	2026-04-30 12:05:57 -07:00
Stan Lee	f3c3eceedf	bugfix	2026-04-30 10:47:23 -07:00
Stan Lee	6aab520cad	simplify	2026-04-30 10:14:42 -07:00
Stan Lee	4600078f55	comments	2026-04-30 10:06:29 -07:00
Stan Lee	f6e6b4afef	better?	2026-04-29 17:23:58 -07:00
Stan Lee	21a2a1b4f8	splitcells was the issue?	2026-04-29 17:07:50 -07:00
Stan Lee	550d48c417	fix value conversion bug	2026-04-29 15:21:29 -07:00
Stan Lee	448ab2a4e7	undo	2026-04-29 11:30:04 -07:00
Stan Lee	3cd792d4d7	warn only on _reg	2026-04-29 11:24:46 -07:00
Stan Lee	325d9b0c0e	edit naming	2026-04-24 17:14:42 -07:00
Stan Lee	90c2bbe1d4	factor offset	2026-04-20 17:26:30 -07:00
Stan Lee	5f538db621	fix	2026-04-20 17:17:37 -07:00
Stan Lee	f377bb04e4	pull main	2026-04-20 16:57:15 -07:00
Akash Levy	c05efa055b	Merge pull request #155 from Silimate/fork-scope ... [CUS-486] Strip $fork scope and N-dim register flattening	2026-04-20 16:43:16 -07:00
Akash Levy	47a5a626e3	Merge pull request #153 from Silimate/reg-rename ... [ENG-1918] Handle edge cases in register renaming	2026-04-20 16:40:16 -07:00
Stan Lee	553ea0a173	edit	2026-04-20 16:11:28 -07:00
Stan Lee	5f663796ad	oops	2026-04-20 15:22:18 -07:00
Stan Lee	38f97edb45	Merge branch 'main' of github.com:silimate/yosys into fork-scope	2026-04-20 15:21:20 -07:00
Stan Lee	1646f7712a	bugfix	2026-04-20 15:12:56 -07:00
Stan Lee	102cbb8c0a	splitcells reg split fix	2026-04-20 15:07:09 -07:00
Stan Lee	fb9a64086e	undo	2026-04-20 14:47:57 -07:00
Stan Lee	1bc33bc8c5	re-trigger	2026-04-20 14:47:43 -07:00
Stan Lee	63b61f04d0	further remove	2026-04-20 13:42:57 -07:00
Stan Lee	608ed37a6d	N-dimensional regs	2026-04-20 13:42:08 -07:00
Akash Levy	78874dfccd	Merge pull request #152 from Silimate/sim ... [ENG-1911] Registers should be annotated every cycle in 'sim'	2026-04-20 12:11:49 -07:00
Stan Lee	8653fea875	fix	2026-04-20 09:45:07 -07:00
Stan Lee	9e05fb7606	comments	2026-04-20 09:40:40 -07:00
Akash Levy	8485d57841	opt_expr for constant comparisons	2026-04-20 02:03:35 -07:00
Stan Lee	3b7613d858	guard for multiple drivers	2026-04-19 21:30:12 -07:00
Stan Lee	d4bfebd0da	offsets supported in reg_rename	2026-04-19 20:00:09 -07:00