mirror of https://github.com/YosysHQ/yosys.git
simplify
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4600078f55
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6aab520cad
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@ -103,18 +103,17 @@ struct RegRenameInstance {
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cellName.erase(reg_pos, 4);
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// Index comes from the right-most brackets
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std::string wireName;
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std::string wireName = cellName;
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int bitIndex = 0;
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size_t last_open = cellName.rfind('[');
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size_t last_close = cellName.rfind(']');
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if (last_open != std::string::npos && last_close != std::string::npos && last_close > last_open) {
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// Check that bracket content is just a single bit index
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// Validate bracket content is just a single bit slice
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std::string inner = cellName.substr(last_open + 1, last_close - last_open - 1);
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wireName = cellName.substr(0, last_open);
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bitIndex = std::stoi(inner);
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} else {
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wireName = cellName;
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bitIndex = 0;
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if (!inner.empty() && inner.find_first_not_of("0123456789") == std::string::npos) {
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wireName = cellName.substr(0, last_open);
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bitIndex = std::stoi(inner);
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}
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}
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// Process Q output connection for the cell
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