mirror of https://github.com/YosysHQ/yosys.git
feat: parallel resim with chunks and bb
This commit is contained in:
Chia-Hsiang Chang
parent
a3d81a6d3f
commit
57c3e484e3
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@ -129,6 +129,8 @@ struct SimShared
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bool fst_noinit = false;
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bool initstate = true;
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bool blackbox_children = false;
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pool<IdString> instance_root_modules;
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double clk_period_override = 0.0;
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};
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void zinit(Const &v)
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@ -336,7 +338,9 @@ struct SimInstance
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{
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Module *mod = module->design->module(cell->type);
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if (mod != nullptr) {
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// Skip recursion into blackbox children, and into cells whose type is also a multi-root top
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if (mod != nullptr && !mod->get_blackbox_attribute(true)
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&& !shared->instance_root_modules.count(mod->name)) {
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dirty_children.insert(new SimInstance(shared, scope + "." + RTLIL::unescape_id(cell->name), mod, cell, this));
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}
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@ -654,6 +658,9 @@ struct SimInstance
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if (cell->type == ID($print))
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return;
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if (shared->blackbox_children)
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return;
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log_error("Unsupported cell type: %s (%s.%s)\n", log_id(cell->type), log_id(module), log_id(cell));
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}
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@ -1409,7 +1416,13 @@ struct SimInstance
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struct SimWorker : SimShared
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{
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std::vector<SimInstance *> tops;
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// Convenience alias kept in sync with tops.front()
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SimInstance *top = nullptr;
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// instance entries: (module name, VCD scope)
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std::vector<std::pair<std::string, std::string>> instance_specs;
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// Resolved Module* per instance_specs entry
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std::vector<RTLIL::Module *> instance_modules;
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pool<IdString> clock, clockn, reset, resetn;
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std::string timescale;
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std::string sim_filename;
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@ -1421,20 +1434,23 @@ struct SimWorker : SimShared
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~SimWorker()
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{
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outputfiles.clear();
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delete top;
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for (auto t : tops) delete t;
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}
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void register_signals()
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{
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next_output_id = 1;
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top->register_signals(top->shared->next_output_id);
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top->build_registers();
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for (auto t : tops) {
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t->register_signals(t->shared->next_output_id);
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t->build_registers();
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}
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}
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void register_output_step(int t)
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{
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std::map<int,Const> data;
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top->register_output_step_values(&data);
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for (auto top : tops)
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top->register_output_step_values(&data);
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output_data.emplace_back(t, data);
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}
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@ -1456,10 +1472,11 @@ struct SimWorker : SimShared
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}
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for(auto& writer : outputfiles)
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writer->write(use_signal);
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if (writeback) {
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pool<Module*> wbmods;
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top->writeback(wbmods);
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for (auto top : tops)
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top->writeback(wbmods);
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}
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}
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@ -1467,47 +1484,50 @@ struct SimWorker : SimShared
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{
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if (gclk)
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step += 1;
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for (auto top : tops) {
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while (1)
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{
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if (debug)
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log("\n-- ph1 --\n");
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while (1)
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{
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if (debug)
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log("\n-- ph1 --\n");
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top->update_ph1();
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top->update_ph1();
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if (debug)
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log("\n-- ph2 --\n");
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if (!top->update_ph2(gclk))
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break;
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}
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if (debug)
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log("\n-- ph2 --\n");
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log("\n-- ph3 --\n");
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if (!top->update_ph2(gclk))
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break;
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top->update_ph3(gclk);
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}
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if (debug)
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log("\n-- ph3 --\n");
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top->update_ph3(gclk);
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}
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void initialize_stable_past()
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{
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for (auto top : tops) {
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while (1)
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{
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if (debug)
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log("\n-- ph1 (initialize) --\n");
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while (1)
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{
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if (debug)
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log("\n-- ph1 (initialize) --\n");
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top->update_ph1();
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top->update_ph1();
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if (debug)
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log("\n-- ph2 (initialize) --\n");
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if (!top->update_ph2(false, true))
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break;
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}
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if (debug)
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log("\n-- ph2 (initialize) --\n");
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if (!top->update_ph2(false, true))
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break;
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log("\n-- ph3 (initialize) --\n");
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top->update_ph3(true);
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}
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if (debug)
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log("\n-- ph3 (initialize) --\n");
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top->update_ph3(true);
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}
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void set_inports(pool<IdString> ports, State value)
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@ -1525,8 +1545,9 @@ struct SimWorker : SimShared
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void run(Module *topmod, int cycle_width, int numcycles)
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{
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log_assert(top == nullptr);
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top = new SimInstance(this, scope, topmod);
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log_assert(tops.empty());
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tops.push_back(new SimInstance(this, scope, topmod));
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top = tops.back();
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register_signals();
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if (debug)
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@ -1585,66 +1606,86 @@ struct SimWorker : SimShared
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void run_cosim_fst(Module *topmod, int numcycles, int log_interval)
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{
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log_assert(top == nullptr);
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log_assert(tops.empty());
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fst = new FstData(sim_filename);
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timescale = fst->getTimescaleString();
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if (scope.empty()) {
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scope = fst->autoScope(topmod);
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if (scope.empty()) {
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log_error("No scope found for module '%s'. Please specify -scope explicitly.\n",
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RTLIL::unescape_id(topmod->name).c_str());
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}
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}
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log("Using scope: \"%s\"\n", scope.c_str());
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top = new SimInstance(this, scope, topmod);
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register_signals();
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std::vector<fstHandle> fst_clock;
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for (auto portname : clock)
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{
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Wire *w = topmod->wire(portname);
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if (!w)
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log_error("Can't find port %s on module %s.\n", log_id(portname), log_id(top->module));
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if (!w->port_input)
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log_error("Clock port %s on module %s is not input.\n", log_id(portname), log_id(top->module));
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fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname));
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if (id==0)
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log_error("Can't find port %s.%s in FST.\n", scope, log_id(portname));
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fst_clock.push_back(id);
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}
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for (auto portname : clockn)
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{
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Wire *w = topmod->wire(portname);
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if (!w)
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log_error("Can't find port %s on module %s.\n", log_id(portname), log_id(top->module));
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if (!w->port_input)
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log_error("Clock port %s on module %s is not input.\n", log_id(portname), log_id(top->module));
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fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname));
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if (id==0)
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log_error("Can't find port %s.%s in FST.\n", scope, log_id(portname));
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fst_clock.push_back(id);
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}
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SigMap sigmap(topmod);
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for (auto wire : topmod->wires()) {
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// Populate fst_inputs for input ports
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if (wire->port_input) {
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fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name));
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if (id != 0) {
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// Case of a regular wire/reg
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top->fst_inputs[wire] = id;
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} else {
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// Not found
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log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(wire->name)));
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// Multi-root mode: instance_modules was resolved in execute() alongside instance_specs
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if (!instance_modules.empty()) {
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for (size_t i = 0; i < instance_modules.size(); i++) {
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const std::string &iscope = instance_specs[i].second;
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Module *m = instance_modules[i];
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log("Using -instance %s at scope \"%s\"\n", instance_specs[i].first.c_str(), iscope.c_str());
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SimInstance *t = new SimInstance(this, iscope, m);
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tops.push_back(t);
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// Drive every port_input from the FST
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for (auto wire : m->wires()) {
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if (!wire->port_input) continue;
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fstHandle id = fst->getHandle(iscope + "." + RTLIL::unescape_id(wire->name));
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if (id != 0) t->fst_inputs[wire] = id;
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}
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t->addAdditionalInputs();
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}
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top = tops.front();
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} else {
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if (scope.empty()) {
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scope = fst->autoScope(topmod);
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if (scope.empty()) {
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log_error("No scope found for module '%s'. Please specify -scope explicitly.\n",
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RTLIL::unescape_id(topmod->name).c_str());
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}
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}
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log("Using scope: \"%s\"\n", scope.c_str());
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tops.push_back(new SimInstance(this, scope, topmod));
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top = tops.back();
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for (auto portname : clock)
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{
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Wire *w = topmod->wire(portname);
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if (!w)
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log_error("Can't find port %s on module %s.\n", log_id(portname), log_id(top->module));
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if (!w->port_input)
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log_error("Clock port %s on module %s is not input.\n", log_id(portname), log_id(top->module));
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fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname));
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if (id==0)
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log_error("Can't find port %s.%s in FST.\n", scope, log_id(portname));
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fst_clock.push_back(id);
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}
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for (auto portname : clockn)
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{
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Wire *w = topmod->wire(portname);
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if (!w)
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log_error("Can't find port %s on module %s.\n", log_id(portname), log_id(top->module));
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if (!w->port_input)
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log_error("Clock port %s on module %s is not input.\n", log_id(portname), log_id(top->module));
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fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname));
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if (id==0)
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log_error("Can't find port %s.%s in FST.\n", scope, log_id(portname));
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fst_clock.push_back(id);
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}
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for (auto wire : topmod->wires()) {
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// Populate fst_inputs for input ports
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if (wire->port_input) {
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fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name));
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if (id != 0) {
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// Case of a regular wire/reg
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top->fst_inputs[wire] = id;
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} else {
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// Not found
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log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(wire->name)));
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}
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}
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}
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top->addAdditionalInputs();
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}
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top->addAdditionalInputs();
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register_signals();
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uint64_t startCount = 0;
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uint64_t stopCount = 0;
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@ -1705,10 +1746,13 @@ struct SimWorker : SimShared
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cycle,
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(unsigned long)time,
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fst->getTimescaleString());
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bool did_something = top->setInputs();
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// Apply per-cycle FST values to every root
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bool did_something = false;
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for (auto t : tops) if (t->setInputs()) did_something = true;
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if (initial) {
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if (!fst_noinit) did_something |= top->setInitState();
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if (!fst_noinit)
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for (auto t : tops) if (t->setInitState()) did_something = true;
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initialize_stable_past();
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initial = false;
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}
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@ -1716,15 +1760,18 @@ struct SimWorker : SimShared
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update(true);
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// Override register state from VCD every cycle
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if (reg_overwrite && top->setRegisters(time))
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update(true);
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if (reg_overwrite) {
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bool diverged = false;
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for (auto t : tops) if (t->setRegisters(time)) diverged = true;
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if (diverged) update(true);
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}
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register_output_step(time);
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last_time = time;
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bool status = top->checkSignals();
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if (status)
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log_error("Signal difference\n");
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bool status = false;
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for (auto t : tops) status |= t->checkSignals();
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if (status) log_error("Signal difference\n");
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cycle++;
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});
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@ -1754,13 +1801,14 @@ struct SimWorker : SimShared
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void run_cosim_aiger_witness(Module *topmod, int cycle_width)
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{
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log_assert(top == nullptr);
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log_assert(tops.empty());
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if (!multiclock && (clock.size()+clockn.size())==0)
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log_error("Clock signal must be specified.\n");
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if (multiclock && (clock.size()+clockn.size())>0)
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log_error("For multiclock witness there should be no clock signal.\n");
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top = new SimInstance(this, scope, topmod);
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tops.push_back(new SimInstance(this, scope, topmod));
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top = tops.back();
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register_signals();
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std::ifstream mf(map_filename);
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@ -1902,7 +1950,7 @@ struct SimWorker : SimShared
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void run_cosim_btor2_witness(Module *topmod, int cycle_width)
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{
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log_assert(top == nullptr);
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log_assert(tops.empty());
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if (!multiclock && (clock.size()+clockn.size())==0)
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log_error("Clock signal must be specified.\n");
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if (multiclock && (clock.size()+clockn.size())>0)
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@ -1914,7 +1962,8 @@ struct SimWorker : SimShared
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int state = 0;
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int cycle = 0;
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top = new SimInstance(this, scope, topmod);
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tops.push_back(new SimInstance(this, scope, topmod));
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top = tops.back();
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register_signals();
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int prev_cycle = 0;
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int curr_cycle = 0;
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@ -2164,7 +2213,8 @@ struct SimWorker : SimShared
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ReadWitness yw(sim_filename);
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top = new SimInstance(this, scope, topmod);
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tops.push_back(new SimInstance(this, scope, topmod));
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top = tops.back();
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register_signals();
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YwHierarchy hierarchy = prepare_yw_hierarchy(yw);
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@ -2295,9 +2345,9 @@ struct SimWorker : SimShared
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{
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Wire *w = topmod->wire(portname);
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if (!w)
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log_error("Can't find port %s on module %s.\n", log_id(portname), log_id(top->module));
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log_error("Can't find port %s on module %s.\n", log_id(portname), log_id(topmod));
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if (!w->port_input)
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log_error("Clock port %s on module %s is not input.\n", log_id(portname), log_id(top->module));
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log_error("Clock port %s on module %s is not input.\n", log_id(portname), log_id(topmod));
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fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname));
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if (id==0)
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log_error("Can't find port %s.%s in FST.\n", scope, log_id(portname));
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@ -2308,9 +2358,9 @@ struct SimWorker : SimShared
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{
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Wire *w = topmod->wire(portname);
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if (!w)
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log_error("Can't find port %s on module %s.\n", log_id(portname), log_id(top->module));
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log_error("Can't find port %s on module %s.\n", log_id(portname), log_id(topmod));
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if (!w->port_input)
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log_error("Clock port %s on module %s is not input.\n", log_id(portname), log_id(top->module));
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log_error("Clock port %s on module %s is not input.\n", log_id(portname), log_id(topmod));
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fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname));
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if (id==0)
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log_error("Can't find port %s.%s in FST.\n", scope, log_id(portname));
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@ -2505,7 +2555,8 @@ struct VCDWriter : public OutputWriter
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if (!worker->timescale.empty())
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vcdfile << stringf("$timescale 1%s $end\n", worker->timescale);
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worker->top->write_output_header(
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// VCD writer emits one root subtree per top
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for (auto top : worker->tops) top->write_output_header(
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[this](IdString name) { vcdfile << stringf("$scope module %s $end\n", log_id(name)); },
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[this]() { vcdfile << stringf("$upscope $end\n");},
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[this,&use_signal](const char *name, int size, Wire *w, int id, bool is_reg) {
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@ -2679,24 +2730,31 @@ struct AnnotateActivity : public OutputWriter {
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log_debug("Timescale %e seconds extracted from converted VCD file", real_timescale);
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}
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// Compute clock period, find the highest toggling signal and compute its average period
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// Compute clock period: prefer the user override (-clk-period), else auto-detect
|
||||
// from the highest-toggling signal
|
||||
double clk_period;
|
||||
SignalActivityDataMap::iterator itr = dataMap.find(clk);
|
||||
if (itr == dataMap.end()) { // if clock signal can't be identified, set frequency to 1GHz
|
||||
log_warning("Clock signal not found, setting frequency to 1GHz...\n");
|
||||
clk_period = 1.0 / 1.0e9;
|
||||
if (worker->clk_period_override > 0) {
|
||||
clk_period = worker->clk_period_override;
|
||||
} else {
|
||||
std::vector<double_t> &clktoggleCounts = itr->second.toggleCounts;
|
||||
clk_period = real_timescale * (double)max_time / (clktoggleCounts[0] / 2.0);
|
||||
SignalActivityDataMap::iterator itr = dataMap.find(clk);
|
||||
if (itr == dataMap.end()) { // if clock signal can't be identified, set frequency to 1GHz
|
||||
log_warning("Clock signal not found, setting frequency to 1GHz...\n");
|
||||
clk_period = 1.0 / 1.0e9;
|
||||
} else {
|
||||
std::vector<double_t> &clktoggleCounts = itr->second.toggleCounts;
|
||||
clk_period = real_timescale * (double)max_time / (clktoggleCounts[0] / 2.0);
|
||||
}
|
||||
}
|
||||
log_flush();
|
||||
|
||||
double frequency = 1.0 / clk_period;
|
||||
worker->top->module->set_string_attribute("$FREQUENCY", std::to_string(frequency));
|
||||
worker->top->module->set_string_attribute("$DURATION", std::to_string(max_time));
|
||||
std::stringstream ss;
|
||||
ss << std::setprecision(4) << real_timescale;
|
||||
worker->top->module->set_string_attribute("$TIMESCALE", ss.str());
|
||||
for (auto top : worker->tops) {
|
||||
top->module->set_string_attribute("$FREQUENCY", std::to_string(frequency));
|
||||
top->module->set_string_attribute("$DURATION", std::to_string(max_time));
|
||||
top->module->set_string_attribute("$TIMESCALE", ss.str());
|
||||
}
|
||||
if (worker->debug) {
|
||||
log_debug("Max time: %d", max_time);
|
||||
log_debug("Clock period: %f", clk_period);
|
||||
|
|
@ -2706,7 +2764,7 @@ struct AnnotateActivity : public OutputWriter {
|
|||
double totalDuty = 0.0f;
|
||||
|
||||
// TODO make this debug code less messy and more readable.
|
||||
worker->top->write_output_header(
|
||||
for (auto top : worker->tops) top->write_output_header(
|
||||
[&](IdString name) {
|
||||
if (worker->debug)
|
||||
log_debug("module %s", log_id(name));
|
||||
|
|
@ -2795,7 +2853,7 @@ struct FSTWriter : public OutputWriter
|
|||
fstWriterSetPackType(fstfile, FST_WR_PT_FASTLZ);
|
||||
fstWriterSetRepackOnClose(fstfile, 1);
|
||||
|
||||
worker->top->write_output_header(
|
||||
for (auto top : worker->tops) top->write_output_header(
|
||||
[this](IdString name) { fstWriterSetScope(fstfile, FST_ST_VCD_MODULE, stringf("%s",log_id(name)).c_str(), nullptr); },
|
||||
[this]() { fstWriterSetUpscope(fstfile); },
|
||||
[this,&use_signal](const char *name, int size, Wire *w, int id, bool is_reg) {
|
||||
|
|
@ -3084,6 +3142,16 @@ struct SimPass : public Pass {
|
|||
log(" cut every parent<->child boundary in the hierarchy and source both sides from the FST\n");
|
||||
log(" (each instance simulates its own logic only; boundary signals come from VCD)\n");
|
||||
log("\n");
|
||||
log(" -instance <module_name>:<scope>\n");
|
||||
log(" repeatable; each entry roots a SimInstance at the named module with the given\n");
|
||||
log(" VCD scope. Skips traversal from design top; combine with -bb so each root simulates\n");
|
||||
log(" only its own logic with all boundaries sourced from the FST.\n");
|
||||
log("\n");
|
||||
log(" -clk-period <seconds>\n");
|
||||
log(" override the activity-factor clock period (default: auto-detect from highest-\n");
|
||||
log(" toggling signal). Useful when each parallel worker sees only a partial design and\n");
|
||||
log(" the local highest-toggling signal isn't the system clock.\n");
|
||||
log("\n");
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -3279,6 +3347,22 @@ struct SimPass : public Pass {
|
|||
worker.blackbox_children = true;
|
||||
continue;
|
||||
}
|
||||
// -instance <module>:<scope>: register a multi-root spec; resolved to Module* below
|
||||
if (args[argidx] == "-instance" && argidx+1 < args.size()) {
|
||||
std::string spec = args[++argidx];
|
||||
size_t pos = spec.find_last_of(':');
|
||||
if (pos == std::string::npos)
|
||||
log_cmd_error("-instance expects '<module>:<scope>' (got '%s')\n", spec.c_str());
|
||||
worker.instance_specs.emplace_back(spec.substr(0, pos), spec.substr(pos + 1));
|
||||
continue;
|
||||
}
|
||||
// -clk-period <seconds>: bypass the highest-toggling-signal heuristic
|
||||
if (args[argidx] == "-clk-period" && argidx+1 < args.size()) {
|
||||
worker.clk_period_override = atof(args[++argidx].c_str());
|
||||
if (worker.clk_period_override <= 0)
|
||||
log_cmd_error("-clk-period expects a positive number of seconds.\n");
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
extra_args(args, argidx, design);
|
||||
|
|
@ -3289,7 +3373,16 @@ struct SimPass : public Pass {
|
|||
|
||||
Module *top_mod = nullptr;
|
||||
|
||||
if (design->full_selection()) {
|
||||
// Resolve every -instance module
|
||||
if (!worker.instance_specs.empty()) {
|
||||
for (auto &spec : worker.instance_specs) {
|
||||
Module *m = design->module(RTLIL::escape_id(spec.first));
|
||||
if (!m)
|
||||
log_cmd_error("Module '%s' (from -instance) not found in design.\n", spec.first.c_str());
|
||||
worker.instance_modules.push_back(m);
|
||||
worker.instance_root_modules.insert(m->name);
|
||||
}
|
||||
} else if (design->full_selection()) {
|
||||
top_mod = design->top_module();
|
||||
|
||||
if (!top_mod)
|
||||
|
|
@ -3302,6 +3395,9 @@ struct SimPass : public Pass {
|
|||
}
|
||||
|
||||
worker.reg_overwrite = reg_overwrite;
|
||||
// Multi-root (-instance) is only supported in FST/VCD cosim
|
||||
if (!worker.instance_specs.empty() && worker.sim_filename.empty())
|
||||
log_cmd_error("-instance requires FST/VCD cosim (-r <file.vcd|.fst>).\n");
|
||||
if (worker.sim_filename.empty())
|
||||
worker.run(top_mod, cycle_width, numcycles);
|
||||
else {
|
||||
|
|
|
|||
Loading…
Reference in New Issue