mirror of https://github.com/YosysHQ/yosys.git
refactor: style fix
This commit is contained in:
Chia-Hsiang Chang
parent
57c3e484e3
commit
7b2e63ac5b
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@ -658,8 +658,11 @@ struct SimInstance
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if (cell->type == ID($print))
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return;
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if (shared->blackbox_children)
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return;
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if (shared->blackbox_children) {
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Module *m = module->design->module(cell->type);
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if (m && (m->get_blackbox_attribute(true) || shared->instance_root_modules.count(m->name)))
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return;
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}
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log_error("Unsupported cell type: %s (%s.%s)\n", log_id(cell->type), log_id(module), log_id(cell));
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}
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@ -1446,12 +1449,12 @@ struct SimWorker : SimShared
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}
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}
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void register_output_step(int t)
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void register_output_step(int time)
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{
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std::map<int,Const> data;
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for (auto top : tops)
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top->register_output_step_values(&data);
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output_data.emplace_back(t, data);
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for (auto t : tops)
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t->register_output_step_values(&data);
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output_data.emplace_back(time, data);
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}
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void write_output_files()
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@ -1475,8 +1478,8 @@ struct SimWorker : SimShared
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if (writeback) {
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pool<Module*> wbmods;
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for (auto top : tops)
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top->writeback(wbmods);
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for (auto t : tops)
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t->writeback(wbmods);
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}
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}
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@ -1484,49 +1487,49 @@ struct SimWorker : SimShared
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{
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if (gclk)
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step += 1;
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for (auto top : tops) {
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for (auto t : tops) {
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while (1)
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{
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if (debug)
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log("\n-- ph1 --\n");
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top->update_ph1();
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t->update_ph1();
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if (debug)
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log("\n-- ph2 --\n");
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if (!top->update_ph2(gclk))
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if (!t->update_ph2(gclk))
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break;
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}
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if (debug)
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log("\n-- ph3 --\n");
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top->update_ph3(gclk);
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t->update_ph3(gclk);
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}
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}
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void initialize_stable_past()
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{
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for (auto top : tops) {
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for (auto t : tops) {
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while (1)
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{
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if (debug)
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log("\n-- ph1 (initialize) --\n");
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top->update_ph1();
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t->update_ph1();
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if (debug)
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log("\n-- ph2 (initialize) --\n");
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if (!top->update_ph2(false, true))
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if (!t->update_ph2(false, true))
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break;
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}
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if (debug)
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log("\n-- ph3 (initialize) --\n");
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top->update_ph3(true);
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t->update_ph3(true);
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}
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}
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@ -1547,7 +1550,7 @@ struct SimWorker : SimShared
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{
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log_assert(tops.empty());
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tops.push_back(new SimInstance(this, scope, topmod));
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top = tops.back();
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top = tops.front();
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register_signals();
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if (debug)
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@ -1640,7 +1643,7 @@ struct SimWorker : SimShared
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log("Using scope: \"%s\"\n", scope.c_str());
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tops.push_back(new SimInstance(this, scope, topmod));
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top = tops.back();
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top = tops.front();
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for (auto portname : clock)
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{
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@ -1748,11 +1751,13 @@ struct SimWorker : SimShared
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fst->getTimescaleString());
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// Apply per-cycle FST values to every root
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bool did_something = false;
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for (auto t : tops) if (t->setInputs()) did_something = true;
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for (auto t : tops)
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did_something |= t->setInputs();
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if (initial) {
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if (!fst_noinit)
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for (auto t : tops) if (t->setInitState()) did_something = true;
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for (auto t : tops)
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did_something |= t->setInitState();
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initialize_stable_past();
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initial = false;
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}
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@ -1762,7 +1767,8 @@ struct SimWorker : SimShared
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// Override register state from VCD every cycle
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if (reg_overwrite) {
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bool diverged = false;
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for (auto t : tops) if (t->setRegisters(time)) diverged = true;
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for (auto t : tops)
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diverged |= t->setRegisters(time);
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if (diverged) update(true);
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}
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@ -1770,8 +1776,10 @@ struct SimWorker : SimShared
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last_time = time;
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bool status = false;
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for (auto t : tops) status |= t->checkSignals();
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if (status) log_error("Signal difference\n");
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for (auto t : tops)
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status |= t->checkSignals();
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if (status)
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log_error("Signal difference\n");
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cycle++;
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});
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@ -1808,7 +1816,7 @@ struct SimWorker : SimShared
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log_error("For multiclock witness there should be no clock signal.\n");
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tops.push_back(new SimInstance(this, scope, topmod));
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top = tops.back();
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top = tops.front();
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register_signals();
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std::ifstream mf(map_filename);
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@ -1963,7 +1971,7 @@ struct SimWorker : SimShared
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int state = 0;
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int cycle = 0;
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tops.push_back(new SimInstance(this, scope, topmod));
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top = tops.back();
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top = tops.front();
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register_signals();
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int prev_cycle = 0;
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int curr_cycle = 0;
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@ -2214,7 +2222,7 @@ struct SimWorker : SimShared
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ReadWitness yw(sim_filename);
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tops.push_back(new SimInstance(this, scope, topmod));
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top = tops.back();
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top = tops.front();
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register_signals();
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YwHierarchy hierarchy = prepare_yw_hierarchy(yw);
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@ -2556,7 +2564,7 @@ struct VCDWriter : public OutputWriter
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vcdfile << stringf("$timescale 1%s $end\n", worker->timescale);
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// VCD writer emits one root subtree per top
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for (auto top : worker->tops) top->write_output_header(
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for (auto t : worker->tops) t->write_output_header(
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[this](IdString name) { vcdfile << stringf("$scope module %s $end\n", log_id(name)); },
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[this]() { vcdfile << stringf("$upscope $end\n");},
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[this,&use_signal](const char *name, int size, Wire *w, int id, bool is_reg) {
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@ -2750,10 +2758,10 @@ struct AnnotateActivity : public OutputWriter {
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double frequency = 1.0 / clk_period;
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std::stringstream ss;
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ss << std::setprecision(4) << real_timescale;
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for (auto top : worker->tops) {
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top->module->set_string_attribute("$FREQUENCY", std::to_string(frequency));
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top->module->set_string_attribute("$DURATION", std::to_string(max_time));
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top->module->set_string_attribute("$TIMESCALE", ss.str());
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for (auto t : worker->tops) {
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t->module->set_string_attribute("$FREQUENCY", std::to_string(frequency));
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t->module->set_string_attribute("$DURATION", std::to_string(max_time));
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t->module->set_string_attribute("$TIMESCALE", ss.str());
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}
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if (worker->debug) {
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log_debug("Max time: %d", max_time);
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@ -2764,7 +2772,7 @@ struct AnnotateActivity : public OutputWriter {
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double totalDuty = 0.0f;
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// TODO make this debug code less messy and more readable.
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for (auto top : worker->tops) top->write_output_header(
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for (auto t : worker->tops) t->write_output_header(
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[&](IdString name) {
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if (worker->debug)
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log_debug("module %s", log_id(name));
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@ -2852,8 +2860,8 @@ struct FSTWriter : public OutputWriter
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fstWriterSetPackType(fstfile, FST_WR_PT_FASTLZ);
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fstWriterSetRepackOnClose(fstfile, 1);
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for (auto top : worker->tops) top->write_output_header(
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for (auto t : worker->tops) t->write_output_header(
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[this](IdString name) { fstWriterSetScope(fstfile, FST_ST_VCD_MODULE, stringf("%s",log_id(name)).c_str(), nullptr); },
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[this]() { fstWriterSetUpscope(fstfile); },
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[this,&use_signal](const char *name, int size, Wire *w, int id, bool is_reg) {
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@ -3347,7 +3355,9 @@ struct SimPass : public Pass {
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worker.blackbox_children = true;
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continue;
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}
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// -instance <module>:<scope>: register a multi-root spec; resolved to Module* below
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// -instance <module>:<scope>: register a multi-root spec; resolved to Module* below.
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// Split on the last ':' so that hierarchical scopes (which use '.' as separator)
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// are kept intact in the scope half.
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if (args[argidx] == "-instance" && argidx+1 < args.size()) {
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std::string spec = args[++argidx];
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size_t pos = spec.find_last_of(':');
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