mirror of https://github.com/YosysHQ/yosys.git
opt_expr for constant comparisons
This commit is contained in:
Akash Levy
parent
a19dfc535c
commit
8485d57841
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@ -2217,6 +2217,231 @@ skip_alu_split:
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goto next_cell;
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}
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}
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// SILIMATE: Generalized MSB-comparison rule. Recognize the pattern
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// `(unsigned X < {sig, k zero bits})` (and its $ge / $gt / $le siblings)
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// where X is provably bounded by 2^k - 1 (i.e., its bits at positions
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// >= k are constant zero or absent due to a narrower port width).
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// This catches comparators that survive after lowering has stripped
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// the original `(signed X < 0)` signedness annotation.
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//
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// Identities (all unsigned, X bounded by 2^k - 1):
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// $lt(X, {msb, k'b0}) -> Y = msb
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// $ge(X, {msb, k'b0}) -> Y = !msb
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// $gt({msb, k'b0}, X) -> Y = msb
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// $le({msb, k'b0}, X) -> Y = !msb
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{
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IdString cmp = cell->type;
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SigSpec sig_a = cell->getPort(ID::A);
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SigSpec sig_b = cell->getPort(ID::B);
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int a_width = cell->parameters[ID::A_WIDTH].as_int();
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int b_width = cell->parameters[ID::B_WIDTH].as_int();
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bool a_signed = cell->getParam(ID::A_SIGNED).as_bool();
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bool b_signed = cell->getParam(ID::B_SIGNED).as_bool();
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// Only handle unsigned comparisons; signed sign-extension changes the bound.
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if (!a_signed && !b_signed)
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{
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// Detect SigSpec of the form {msb_bit, k_zero_bits} where msb_bit is a
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// non-constant signal bit. Returns (matched, msb_bit, k).
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auto detect_msb_zeros = [](const SigSpec &s, int width) -> std::tuple<bool, SigBit, int> {
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if (width < 1)
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return std::make_tuple(false, SigBit(), 0);
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for (int i = 0; i < width - 1; i++) {
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if (s[i] != RTLIL::State::S0)
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return std::make_tuple(false, SigBit(), 0);
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}
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SigBit msb = s[width - 1];
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if (msb.wire == nullptr)
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return std::make_tuple(false, SigBit(), 0);
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return std::make_tuple(true, msb, width - 1);
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};
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// Check if SigSpec value (unsigned, within its declared width) is
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// bounded by 2^k - 1, i.e., bits at positions [k, width) are all
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// constant zero. Bits beyond `width` (if comparison is wider) are
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// implicit unsigned zero-extension and therefore zero too.
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auto is_bounded_by_2_pow_k = [](const SigSpec &s, int width, int k) -> bool {
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for (int i = k; i < width; i++) {
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if (s[i] != RTLIL::State::S0)
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return false;
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}
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return true;
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};
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auto emit_replace = [&](SigBit y_bit, bool inverted, const std::string &condition) {
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std::string replacement = inverted ? "!Y" : "Y";
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log_debug("Replacing %s cell `%s' (implementing %s) with %s.\n",
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log_id(cell->type), log_id(cell), condition.c_str(), replacement.c_str());
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if (inverted) {
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// SILIMATE: Preserve original cell name on the replacement $logic_not.
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RTLIL::IdString cell_name = cell->name;
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module->rename(cell->name, NEW_ID);
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module->addLogicNot(cell_name, y_bit, cell->getPort(ID::Y), false, cell->get_src_attribute());
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} else {
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SigSpec replace_sig(RTLIL::State::S0, GetSize(cell->getPort(ID::Y)));
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replace_sig[0] = y_bit;
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module->connect(cell->getPort(ID::Y), replace_sig);
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}
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module->remove(cell);
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did_something = true;
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};
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// Case 1: structured operand on the B side, free operand on A.
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if (cmp == ID($lt) || cmp == ID($ge)) {
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bool m;
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SigBit msb;
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int k;
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std::tie(m, msb, k) = detect_msb_zeros(sig_b, b_width);
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if (m && is_bounded_by_2_pow_k(sig_a, a_width, k)) {
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std::string cond = stringf("unsigned X %s {Y, %d'b0}",
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cmp == ID($lt) ? "<" : ">=", k);
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emit_replace(msb, /*inverted=*/cmp == ID($ge), cond);
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goto next_cell;
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}
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}
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// Case 2: structured operand on the A side, free operand on B.
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if (cmp == ID($gt) || cmp == ID($le)) {
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bool m;
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SigBit msb;
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int k;
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std::tie(m, msb, k) = detect_msb_zeros(sig_a, a_width);
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if (m && is_bounded_by_2_pow_k(sig_b, b_width, k)) {
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std::string cond = stringf("unsigned {Y, %d'b0} %s X", k,
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cmp == ID($gt) ? ">" : "<=");
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emit_replace(msb, /*inverted=*/cmp == ID($le), cond);
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goto next_cell;
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}
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}
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}
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}
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// SILIMATE: Recognize the lowered form of `(signed X < -1)` after
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// signedness has been stripped. Verific lowers it to:
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// $lt(unsigned A, unsigned B) with A_WIDTH == B_WIDTH = N >= 2,
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// A = {1'b1, X[N-2:0]} (MSB forced to 1)
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// B = {X[N-1], (N-1)'b1 } (low N-1 bits forced to 1)
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// where X is one coherent N-bit slice of a single wire.
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//
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// Truth table:
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// X[N-1] == 0 -> A >= 2^(N-1) > B = 2^(N-1)-1, so A < B = 0
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// X[N-1] == 1 -> A = 2^(N-1) + X[N-2:0], B = 2^N - 1,
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// A < B iff X[N-2:0] != all 1s
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//
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// So Y = X[N-1] AND ~&X[N-2:0]
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// = X[N-1] AND |~X[N-2:0] (the "reduce_or" form)
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//
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// Mirror cases:
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// $gt(A, B) == $lt(B, A) -> swap operands
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// $ge(A, B) == !$lt(A, B) -> invert output
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// $le(A, B) == !$gt(A, B) == !$lt(B,A) -> swap + invert
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{
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IdString cmp = cell->type;
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SigSpec sig_a = cell->getPort(ID::A);
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SigSpec sig_b = cell->getPort(ID::B);
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int a_width = cell->parameters[ID::A_WIDTH].as_int();
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int b_width = cell->parameters[ID::B_WIDTH].as_int();
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bool a_signed = cell->getParam(ID::A_SIGNED).as_bool();
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bool b_signed = cell->getParam(ID::B_SIGNED).as_bool();
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if (!a_signed && !b_signed && a_width == b_width && a_width >= 2)
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{
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int N = a_width;
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// Try to match: lo = {1'b1, X[N-2:0]}, hi = {X[N-1], (N-1)'b1}.
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// On success returns (msb_bit, x_low_sigspec) with x_low = X[N-2:0].
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auto try_match_lt_neg1 =
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[&](const SigSpec &lo, const SigSpec &hi) -> std::tuple<bool, SigBit, SigSpec> {
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if (lo[N - 1] != RTLIL::State::S1)
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return std::make_tuple(false, SigBit(), SigSpec());
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for (int i = 0; i < N - 1; i++) {
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if (hi[i] != RTLIL::State::S1)
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return std::make_tuple(false, SigBit(), SigSpec());
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}
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SigBit msb = hi[N - 1];
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if (msb.wire == nullptr)
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return std::make_tuple(false, SigBit(), SigSpec());
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int base = msb.offset - (N - 1);
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if (base < 0)
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return std::make_tuple(false, SigBit(), SigSpec());
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for (int i = 0; i < N - 1; i++) {
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SigBit b = lo[i];
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if (b.wire != msb.wire)
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return std::make_tuple(false, SigBit(), SigSpec());
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if (b.offset != base + i)
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return std::make_tuple(false, SigBit(), SigSpec());
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}
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SigSpec x_low(msb.wire, base, N - 1);
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return std::make_tuple(true, msb, x_low);
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};
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auto emit_lt_neg1 = [&](SigBit msb, SigSpec x_low, bool inverted,
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const std::string &condition) {
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std::string replacement = inverted
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? "!(X[N-1] && !&X[N-2:0])"
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: "X[N-1] && !&X[N-2:0]";
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log_debug("Replacing %s cell `%s' (implementing %s) with %s.\n",
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log_id(cell->type), log_id(cell), condition.c_str(),
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replacement.c_str());
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// SILIMATE: Preserve original cell name on the kept replacement
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// cell, and derive intermediate wire/cell names from it via
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// NEW_ID3_SUFFIX so the resulting netlist stays readable.
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RTLIL::IdString cell_name = cell->name;
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module->rename(cell->name, NEW_ID);
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std::string src = cell->get_src_attribute();
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// reduce_and(X[N-2:0]) -> w_red
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Wire *w_red = module->addWire(NEW_ID3_SUFFIX("ry"));
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module->addReduceAnd(NEW_ID3_SUFFIX("r"), x_low, w_red,
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false, src);
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// !reduce_and(...) -> w_some_zero
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Wire *w_some_zero = module->addWire(NEW_ID3_SUFFIX("ny"));
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module->addLogicNot(NEW_ID3_SUFFIX("n"), SigSpec(w_red),
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SigSpec(w_some_zero), false, src);
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// X[N-1] AND w_some_zero -> result
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if (inverted) {
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Wire *w_and = module->addWire(NEW_ID3_SUFFIX("ay"));
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module->addAnd(NEW_ID3_SUFFIX("a"), SigSpec(msb),
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SigSpec(w_some_zero), SigSpec(w_and), false, src);
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module->addLogicNot(cell_name, SigSpec(w_and),
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cell->getPort(ID::Y), false, src);
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} else {
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module->addAnd(cell_name, SigSpec(msb), SigSpec(w_some_zero),
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cell->getPort(ID::Y), false, src);
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}
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module->remove(cell);
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did_something = true;
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};
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if (cmp == ID($lt) || cmp == ID($ge)) {
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bool m;
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SigBit msb;
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SigSpec x_low;
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std::tie(m, msb, x_low) = try_match_lt_neg1(sig_a, sig_b);
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if (m) {
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std::string cond = stringf("unsigned X %s -1 (signed-stripped)",
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cmp == ID($lt) ? "<" : ">=");
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emit_lt_neg1(msb, x_low, /*inverted=*/cmp == ID($ge), cond);
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goto next_cell;
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}
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}
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if (cmp == ID($gt) || cmp == ID($le)) {
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bool m;
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SigBit msb;
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SigSpec x_low;
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std::tie(m, msb, x_low) = try_match_lt_neg1(sig_b, sig_a);
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if (m) {
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std::string cond = stringf("-1 %s unsigned X (signed-stripped)",
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cmp == ID($gt) ? ">" : "<=");
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emit_lt_neg1(msb, x_low, /*inverted=*/cmp == ID($le), cond);
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goto next_cell;
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}
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}
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}
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}
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}
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next_cell:;
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@ -0,0 +1,50 @@
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module top(
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a, b, x,
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o1_1, o1_2, o1_3, o1_4,
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o2_1, o2_2, o2_3, o2_4,
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o3_1, o3_2, o3_3, o3_4,
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o4_1, o4_2, o4_3, o4_4,
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o5_1, o5_2, o5_3, o5_4
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);
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input [3:0] a;
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input b;
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input [7:0] x;
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output o1_1, o1_2, o1_3, o1_4;
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output o2_1, o2_2, o2_3, o2_4;
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output o3_1, o3_2, o3_3, o3_4;
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output o4_1, o4_2, o4_3, o4_4;
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output o5_1, o5_2, o5_3, o5_4;
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// RHS = {b, 4'b0000}: same width as `a`, lower bits zero.
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assign o1_1 = a < {b, 4'b0000};
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assign o1_2 = a >= {b, 4'b0000};
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assign o1_3 = {b, 4'b0000} > a;
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assign o1_4 = {b, 4'b0000} <= a;
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// RHS = {b, 5'b00000}: wider than `a`; `a` zero-extends to fit.
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assign o2_1 = a < {b, 5'b00000};
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assign o2_2 = a >= {b, 5'b00000};
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assign o2_3 = {b, 5'b00000} > a;
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assign o2_4 = {b, 5'b00000} <= a;
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// LHS = {1'b0, a}: explicit zero-extend on the bounded operand.
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assign o3_1 = {1'b0, a} < {b, 4'b0000};
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assign o3_2 = {1'b0, a} >= {b, 4'b0000};
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assign o3_3 = {b, 4'b0000} > {1'b0, a};
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assign o3_4 = {b, 4'b0000} <= {1'b0, a};
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// Lowered form of `(signed x < -1)` after sign-stripping:
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// A = {1'b1, x[N-2:0]}, B = {x[N-1], (N-1)'b1}, both unsigned.
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// Expected: Y = x[N-1] && ~&x[N-2:0]
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assign o4_1 = {1'b1, x[6:0]} < {x[7], 7'b1111111};
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assign o4_2 = {1'b1, x[6:0]} >= {x[7], 7'b1111111};
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assign o4_3 = {x[7], 7'b1111111} > {1'b1, x[6:0]};
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assign o4_4 = {x[7], 7'b1111111} <= {1'b1, x[6:0]};
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// Same pattern at width = 2 (smallest viable N).
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assign o5_1 = {1'b1, x[0]} < {x[1], 1'b1};
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assign o5_2 = {1'b1, x[0]} >= {x[1], 1'b1};
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assign o5_3 = {x[1], 1'b1} > {1'b1, x[0]};
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assign o5_4 = {x[1], 1'b1} <= {1'b1, x[0]};
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endmodule
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@ -0,0 +1,4 @@
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read_verilog opt_expr_cmp_msb.v
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 0 t:$gt t:$ge t:$lt t:$le
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