mirror of https://github.com/YosysHQ/yosys.git
splitcells reg split fix
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@ -202,22 +202,19 @@ struct SplitcellsWorker
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Wire *w = raw_q[slice_lsb].wire;
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std::string wire_name = w->name.str();
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// Extract bit offset from the wire (ex: 0)
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int bit_offset = user_index(slice_lsb);
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// Concatenate wire index (ex: \Memory[0] -> [0]) to the bit offset (ex: [0][bit])
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size_t bracket_pos = wire_name.find('[');
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if (bracket_pos != std::string::npos) {
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wire_indices = wire_name.substr(bracket_pos) + stringf(
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"%c%d%c", format[0], bit_offset, format[1]);
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"%c%d%c", format[0], slice_lsb, format[1]);
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} else { // no brackets, so no concatenation
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wire_indices = stringf(
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"%c%d%c", format[0], bit_offset, format[1]);
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"%c%d%c", format[0], slice_lsb, format[1]);
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}
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} else {
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// Fallback
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wire_indices = stringf(
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"%c%d%c", format[0], name_lsb, format[1]);
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"%c%d%c", format[0], slice_lsb, format[1]);
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}
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// Construct uniquified name by concatenating the base name with the wire indices
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slice_name = module->uniquify(base_name + wire_indices);
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