mirror of https://github.com/YosysHQ/yosys.git
chore: log error when no scope found
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@ -1612,7 +1612,11 @@ struct SimWorker : SimShared
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for (auto wire : m->wires()) {
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if (!wire->port_input) continue;
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fstHandle id = fst->getHandle(iscope + "." + RTLIL::unescape_id(wire->name));
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if (id != 0) t->fst_inputs[wire] = id;
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if (id == 0) {
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log_error("Can't find port '%s' on module '%s' in FST.\n",
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(iscope + "." + RTLIL::unescape_id(wire->name)).c_str(), RTLIL::unescape_id(m->name).c_str());
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}
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t->fst_inputs[wire] = id;
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}
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t->addAdditionalInputs();
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}
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