| .. |
|
0_examples_top.sch
|
fix find_closest_dataset() if log scale axes are used
|
2022-09-13 13:39:25 +02:00 |
|
LCC_instances.sch
|
annotation of voltage and currents in (nested) LCC instances
|
2022-10-16 13:08:52 +02:00 |
|
LCC_instances.sym
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
LM5134A.sch
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
LM5134A.sym
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
MSA-2643.sch
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
Q1.sch
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
Q1.sym
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
Q2.sch
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
Q2.sym
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
TwoStageAmp.sch
|
Added various procedures to select flat / hierarchical instances and re-route a terminal to a different net. reroute_inst -> change a pin connection, reroute_net -> change net updating all connected components. "xschem instances_to_net", "xschem instance_nodemap", "xschem instance_pin_coord" new query commands added. "xschem get expandlabel node" renamed to "xschem expandlabel node".
|
2020-11-26 03:46:55 +01:00 |
|
an2.sym
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
and.sym
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
ao21.sym
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
buf.sym
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
bus_keeper.sch
|
annotation of voltage and currents in (nested) LCC instances
|
2022-10-16 13:08:52 +02:00 |
|
classD_amp.sch
|
wire labels: default name set to p1 instead of l1, so it will not clash with typical inductor names
|
2022-10-12 16:36:56 +02:00 |
|
classD_amp.sym
|
added class D amplifier example
|
2022-02-15 17:20:15 +01:00 |
|
cmos_example.sch
|
netlister code rewrite to allow any combination of pass-through symbols
|
2022-10-10 14:54:32 +02:00 |
|
cmos_example.sym
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
cmos_inv.sch
|
annotation of voltage and currents in (nested) LCC instances
|
2022-10-16 13:08:52 +02:00 |
|
cmos_inv.sym
|
new find_inst_to_be_redrawn() implementation to recalculate area to be redrawn with/without show net names on symbol pins, simplified new_window() call in callback `x` command, code formatting in globals.c, added xschem get [xy]origin commands
|
2021-12-03 19:15:07 +01:00 |
|
diode_1.sch
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
diode_1.sym
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
dlatch.sch
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
dlatch.sym
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
doublepin.sch
|
better check_unique_names() and hash_all_names() implementation (do not skip label instances or instances with no format attr). Button click focuses main drawing window even if autofocus_mainwindow is set to 0, to avoid losing keyboard focus forever if TAB is pressed.
|
2022-10-12 11:56:02 +02:00 |
|
doublepin.sym
|
refactoring of netlister code
|
2022-10-07 23:29:42 +02:00 |
|
flop.sch
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
flop.sym
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
greycnt.sch
|
fix repeated character in RE, fix changed syntax in verilog example
|
2020-11-28 20:08:40 +01:00 |
|
greycnt.sym
|
enable "preserve unchanged props" checkbutton in text edit prop dialog box
|
2020-08-24 16:21:50 +02:00 |
|
inv_bsource.sym
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
lightning.sch
|
"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
|
2020-09-30 00:30:48 +02:00 |
|
lm317.sch
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
lm317.sym
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
lm324.sym
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
lm337.sch
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
lm337.sym
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
loading.sch
|
look for inutile stimuli files in schematic directory instead of in simulation directory
|
2022-09-13 18:53:17 +02:00 |
|
loading.sym
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
loading.vhdl
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
mos_power_ampli.sch
|
use sim_pinnumber for port ordering in simulation netlists and leave pinnumber for package pin position. These two collide, for example in spice port ordering vs (transistor problem) device package pinnumbers. Dont load graphs in lcc symbols
|
2022-10-17 12:05:54 +02:00 |
|
mos_power_ampli.sym
|
changed @schname to @schname_ext and added @schname that expands to the schematic name containing the instance, with no extension (no .sch)
|
2022-08-10 08:38:49 +02:00 |
|
mos_power_ampli_extracted.sch
|
add test_extracted_netlist circuit example
|
2022-02-18 15:11:44 +01:00 |
|
mos_power_ampli_extracted.sym
|
add test_extracted_netlist circuit example
|
2022-02-18 15:11:44 +01:00 |
|
nand.sym
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
nand2.sch
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
nand2.sym
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
nand3.sym
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
nd2-1.sym
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
ne555.sym
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
not.sym
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
nr2-1.sym
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
or2.sym
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
osc.sch
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
osc.sym
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
plot_manipulation.sch
|
graph axes in engineering notation (20u, 10p, 3k), fix an issue in graph panning with button1 mouse; ngspice:: get_current, get_voltage, get_diff_voltage, get_node embedded into xschem.tcl, to_eng tcl procedure to convert number to engineering form.
|
2022-09-28 19:14:31 +02:00 |
|
plot_manipulation.sym
|
added plot_manipulation.sch example showing how to manually create an ngspice plot collecting data from multiple operating point sims. the syntax is so difficult to remember so i keep a working example available here.
|
2020-12-09 13:53:32 +01:00 |
|
poweramp.sch
|
allow spice multipliers in numbers (20u, 10k, 20p) in graph expressions
|
2022-09-22 21:12:40 +02:00 |
|
poweramp.sym
|
do a tcl evaluation of the "schematic" attribute of a symbol if the attribute is within a tcleval(...) expression. This way tcl variables/expressions can be used to determine the schematic to descend into when traversing/netlisting. example: schematic=tcleval(poweramp_${::mode}.sch).
|
2021-06-17 00:25:39 +02:00 |
|
poweramp_xyce.sch
|
example schematics formatting
|
2022-02-16 01:08:16 +01:00 |
|
poweramp_xyce.sym
|
xyce quircks/integration for ac analysis, refuse to stretch unscalable images, more example schematics
|
2022-02-03 00:40:59 +01:00 |
|
pump.sch
|
look for inutile stimuli files in schematic directory instead of in simulation directory
|
2022-09-13 18:53:17 +02:00 |
|
pump.sym
|
snap and grid entries will not annoyingly receive keyboard focus with TAB key
|
2020-08-19 15:08:35 +02:00 |
|
rcline.sch
|
fix correct version syntax when saving in file
|
2020-12-17 02:01:38 +01:00 |
|
rcline.sym
|
get_tok_value: even if called with "with_quotes=2" do not skip unescaped backslashes that are outside "quotes". Added dynamic netlisting test circuit in examples
|
2020-10-23 23:17:55 +02:00 |
|
real_capa.sch
|
look for inutile stimuli files in schematic directory instead of in simulation directory
|
2022-09-13 18:53:17 +02:00 |
|
real_capa.sym
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
rlc.sch
|
remove "m=1" in xyce spice netlists as xyce does not handle m param. Translate spice_probe ".save" to xyce ".print tran", handle different hierarchical expansion of voltage/current nodes in xyce for hierarchical ammeter/spice_probe probes
|
2020-12-17 18:26:46 +01:00 |
|
rlc.sym
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
sr_flop.sch
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
sr_flop.sym
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
stimuli.greycnt
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
switch_rreal.sch
|
look for inutile stimuli files in schematic directory instead of in simulation directory
|
2022-09-13 18:53:17 +02:00 |
|
switch_rreal.sym
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
tesla.sch
|
xyce quircks/integration for ac analysis, refuse to stretch unscalable images, more example schematics
|
2022-02-03 00:40:59 +01:00 |
|
tesla.sym
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
test.sch
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
test2.sch
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
test_ac.sch
|
updated example schematics to new annotate / raw file loading methods
|
2022-09-20 18:25:31 +02:00 |
|
test_ac.sym
|
ac analysis in graphs (mag + phase, log axis)
|
2022-02-02 18:33:16 +01:00 |
|
test_ac_xyce.sch
|
xyce quircks/integration for ac analysis, refuse to stretch unscalable images, more example schematics
|
2022-02-03 00:40:59 +01:00 |
|
test_ac_xyce.sym
|
xyce quircks/integration for ac analysis, refuse to stretch unscalable images, more example schematics
|
2022-02-03 00:40:59 +01:00 |
|
test_backannotated_subckt.sch
|
improve test_backannotated_subckt.sch example, remove dbg messages
|
2022-08-23 10:44:00 +02:00 |
|
test_backannotated_subckt.sym
|
get_tok_value: even if called with "with_quotes=2" do not skip unescaped backslashes that are outside "quotes". Added dynamic netlisting test circuit in examples
|
2020-10-23 23:17:55 +02:00 |
|
test_doublepin.sch
|
make examples/test_doublepin.sch compile with no errors with ngspice, ghdl and iverilog, this is a test schematic to validate pass-through symbols
|
2022-10-11 14:25:58 +02:00 |
|
test_doublepin.sym
|
add another missing symbol file in examples
|
2022-02-17 02:35:41 +01:00 |
|
test_extracted_netlist.sch
|
updated test schematics to use new xschem annotate_op instead of ngspice::annotate
|
2022-09-21 18:38:53 +02:00 |
|
test_extracted_netlist.sym
|
add test_extracted_netlist circuit example
|
2022-02-18 15:11:44 +01:00 |
|
test_lm324.sch
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
test_lm324.sym
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
test_ne555.sch
|
images (rotated,flipped as the symbol) in symbols
|
2022-01-24 22:58:30 +01:00 |
|
test_ne555.sym
|
images (rotated,flipped as the symbol) in symbols
|
2022-01-24 22:58:30 +01:00 |
|
xcross.sch
|
better check_unique_names() and hash_all_names() implementation (do not skip label instances or instances with no format attr). Button click focuses main drawing window even if autofocus_mainwindow is set to 0, to avoid losing keyboard focus forever if TAB is pressed.
|
2022-10-12 11:56:02 +02:00 |
|
xcross.sym
|
persists highlights on instances: remove highlighted instance from hash if user selects and presses ctrl-k as it is done for nets. Avoid instance highlight to also highlight net with identical name (example instance x1 and net x1). Verilog and Vhdl netlists handle duplicated (pass-through) pins
|
2022-10-11 13:12:17 +02:00 |
|
xnor.sch
|
populating xschem git repo
|
2020-08-08 15:47:34 +02:00 |
|
xnor.sym
|
added in the menu the (undocumented) "propagate-highlight" function (propagate through conductive elements)
|
2021-01-02 20:33:34 +01:00 |
b0359d880a