improve test_backannotated_subckt.sch example, remove dbg messages

This commit is contained in:
Stefan Frederik 2022-08-23 10:44:00 +02:00
parent 0f5881cd61
commit dffc266e0d
2 changed files with 11 additions and 7 deletions

View File

@ -1656,7 +1656,7 @@ void print_spice_subckt(FILE *fd, int symbol)
const char *tclres;
my_strdup(103, &format1, get_tok_value(xctx->sym[symbol].prop_ptr,"format",2));
dbg(0, "print_spice_subckt(): format1=%s\n", format1);
dbg(1, "print_spice_subckt(): format1=%s\n", format1);
if(strstr(format1, "tcleval(") == format1) {
tclres = tcl_hook2(&format1);
if(!strcmp(tclres, "?\n")) my_strdup(1529, &format, format1 + 8);
@ -1664,7 +1664,7 @@ void print_spice_subckt(FILE *fd, int symbol)
} else {
my_strdup(1530, &format, format1);
}
dbg(0, "print_spice_subckt(): format=%s\n", format);
dbg(1, "print_spice_subckt(): format=%s\n", format);
if( format==NULL ) {
my_free(1012, &format);
return; /* no format */

View File

@ -1,4 +1,4 @@
v {xschem version=2.9.8 file_version=1.2 }
v {xschem version=3.1.0 file_version=1.2 }
G {}
K {}
V {}
@ -12,18 +12,22 @@ attribute to calculate "Res" and "Cap" subcircuit parameters from W and L
instance parameters.
Tcl scripts can be loaded in xcshemrc by appending a tcl file name to variable
tcl_files.} 40 -390 2 1 0.5 0.5 {layer=8 }
T {proc calc_rc \{ L W \} \{ return "Res=[expr 1200*$L/$W] Cap=[expr 1e-3*$W*$L]"\} } 30 -320 0 0 0.4 0.4 { font=monospace}
T {proc calc_rc \{ L W \} \{
if \{[catch \{expr 1200*$L/$W\} res]\} \{set res -1\}
if \{[catch \{expr 1e-3*$W*$L\} cap]\} \{set cap -1\}
return "Res=$res Cap=$cap"
\} } 270 -370 0 0 0.4 0.4 { font=monospace}
T {Dynamic calculation of subcircuit parameters} 80 -730 0 0 0.8 0.8 {}
N 140 -130 140 -100 { lab=0}
N 140 -210 160 -210 { lab=IN}
N 140 -210 140 -190 { lab=IN}
C {lab_pin.sym} 620 -190 0 1 {name=p1 lab=OUT}
C {lab_pin.sym} 320 -190 0 0 {name=p2 lab=IN}
C {lab_pin.sym} 670 -150 0 1 {name=p1 lab=OUT}
C {lab_pin.sym} 370 -150 0 0 {name=p2 lab=IN}
C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"}
C {vsource.sym} 140 -160 0 0 {name=V1 value="pwl 0 0 10n 0 11n 5"}
C {lab_pin.sym} 140 -100 0 0 {name=l2 sig_type=std_logic lab=0}
C {lab_pin.sym} 160 -210 0 1 {name=p3 lab=IN}
C {rcline.sym} 470 -190 0 0 {name=x1 L=1e-4 W=0.5e-6
C {rcline.sym} 520 -150 0 0 {name=x1 L=1e-4 W=0.5e-6
}
C {code_shown.sym} 890 -190 0 0 {name=STIMULI
only_toplevel=false