populating xschem git repo

This commit is contained in:
Stefan SChippers 2020-08-08 15:47:34 +02:00
parent 7fe79fb2bf
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AUTHORS Normal file
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Stefan Frederik Schippers
stefan.schippers@gmail.com

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COPYING Normal file
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GNU GENERAL PUBLIC LICENSE
Version 2, June 1991
Copyright (C) 1989, 1991 Free Software Foundation, Inc.,
51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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Ty Coon, President of Vice
This General Public License does not permit incorporating your program into
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consider it more useful to permit linking proprietary applications with the
library. If this is what you want to do, use the GNU Lesser General
Public License instead of this License.

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Changelog Normal file

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INSTALL Normal file
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1. requirements
- C89 compiler
- awk (tested with mawk and gawk)
- tcl/tk (tested with 8.4, 8.5 and 8.6)
- Xlib, Xpm
- bison
- flex
- optional: cairo (for fancier text rendering)
- optional: xcb
- optional: xrender
2. compiling
./configure && make
See ./configure --help for configure-time options.
3. running from source (does not require installation)
cd src && ./xschem
4. installation
make install
or
make install DESTDIR=/tmp/packaging

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Makefile Normal file
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all: FORCE
cd src && $(MAKE)
cd xschem_library && $(MAKE)
cd doc && $(MAKE)
cd src/utile && $(MAKE)
clean: FORCE
cd src && $(MAKE) clean
cd xschem_library && $(MAKE) clean
cd doc && $(MAKE) clean
cd src/utile && $(MAKE) clean
distclean: FORCE
$(MAKE) clean ; true
cd src && $(MAKE) distclean
cd xschem_library && $(MAKE) distclean
cd doc && $(MAKE) distclean
cd src/utile && $(MAKE) distclean
rm -f Makefile.conf config.h src/Makefile
cd scconfig && make distclean
install: FORCE
cd src && $(MAKE) install
cd xschem_library && $(MAKE) install
cd doc && $(MAKE) install
cd src/utile && $(MAKE) install
uninstall: FORCE
cd src && $(MAKE) uninstall
cd xschem_library && $(MAKE) uninstall
cd doc && $(MAKE) uninstall
cd src/utile && $(MAKE) uninstall
FORCE:

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put /local/xschem/cflags [@
@cc/cflags@
@?libs/gui/cairo/cflags@
@?libs/gui/xrender/cflags@
@?libs/gui/xcb/cflags@
@?libs/gui/xcb_render/cflags@
@?libs/gui/xgetxcbconnection/cflags@
@libs/gui/xpm/cflags@
@libs/script/tk/cflags@
@libs/script/tcl/cflags@
@]
put /local/xschem/ldflags [@
@cc/ldflags@
-lm
@?libs/gui/cairo/ldflags@
@?libs/gui/xrender/ldflags@
@?libs/gui/xcb/ldflags@
@?libs/gui/xcb_render/ldflags@
@?libs/gui/xgetxcbconnection/ldflags@
@libs/gui/xpm/ldflags@
@libs/script/tk/ldflags@
@libs/script/tcl/ldflags@
@]
uniq /local/xschem/cflags
uniq /local/xschem/ldflags
gsub /local/xschem/cflags {\n} { }
gsub /local/xschem/ldflags {\n} { }
print [@###############################################################
# Generated by scconfig - DO NOT EDIT - will be overwritten #
# Source: Makefile.conf.in; to regenerate run ./configure #
###############################################################
PREFIX=@/local/xschem/prefix@
CC=@cc/cc@
CFLAGS=@/local/xschem/cflags@
LDFLAGS=@/local/xschem/ldflags@
BINDIR=$(DESTDIR)$(install_root)$(PREFIX)/bin
SHAREDIR=$(DESTDIR)$(install_root)$(PREFIX)/share
DOCDIR=$(DESTDIR)$(install_root)$(PREFIX)/share/doc
XSHAREDIR=$(SHAREDIR)/xschem
XDOCDIR=$(DOCDIR)/xschem
MANDIR=$(SHAREDIR)/man
USER_CONF_DIR=@/local/xschem/user-conf-dir@
SCCBOX=$(ROOT)/scconfig/sccbox
## specify user schematic/symbol libraries;
## you may redefine it later in .xschem or xschemrc startup files
user_library_dir=@/local/xschem/user-lib-path@
## specify system-wide symbol libraries;
## you may redefine it later in ~/.xschem/xschemrc or
## `pwd`/.xschemrc startup files
system_library_dir=$(DESTDIR)$(install_root)@/local/xschem/sys-lib-path@
## default search path
xschem_library_path=@/local/xschem/xschem-lib-path@
@]

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README Normal file
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XSCHEM : schematic capture and netlisting EDA tool
Xschem is a schematic capture program, it allows creation of hierarchical representation
of circuits with a top down approach . By focusing on interfaces, hierarchy and instance
properties a complex system can be described in terms of simpler building blocks. A VHDL
or Verilog or Spice netlist can be generated from the drawn schematic, allowing the
simulation of the circuit. Key feature of the program is its drawing engine written in C
and using directly the Xlib drawing primitives; this gives very good speed performance,
even on very big circuits. The user interface is built with the Tcl-Tk toolkit, tcl is
also the extension language used.
DOCUMENTATION AND MANUAL
http://repo.hu/projects/xschem
BUILDING & INSTALLING
Please read the instructions in file INSTALL.
SUBDIRECTORIES
doc: xschem homepage, reference manual and man pages
scconfig: the whole ./configure system (all dependencies included)
src: C source for the xschem executable and scripts for GUI and I/O
src/utile: stimuli generator/converter scripts
xschem_library: standard symbol libs and example libs

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1. requirements
- Windows 10
- ActiveState TCL/TK 8.69 x64 (https://www.activestate.com/products/tcl/)
- Gawk for Windows (Add directory of awk.exe to PATH)
- NGSpice for Windows
2. Install Tree
C:/Program Files/XSchem/bin - Binaries (executable file).
C:/Program Files/XSchem/doc - Various documentation.
C:/Program Files/XSchem/share - default share directory containing systemlib, utile, xschem.tcl, xschemrc and *.awk (can be overriden with XSCHEM_SHARE_DIR)
C:/Program Files/XSchem/xschem_library - XSchem library consisting of .sch and .sym
C:/Users/<YourUserName>/xschem - User configuration directory
It's important to maintain this Install tree for XSchem to work correctly

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XSCHEM : schematic capture and netlisting EDA tool
Xschem is a schematic capture program, it allows creation of hierarchical representation
of circuits with a top down approach . By focusing on interfaces, hierarchy and instance
properties a complex system can be described in terms of simpler building blocks. A VHDL
or Verilog or Spice netlist can be generated from the drawn schematic, allowing the
simulation of the circuit. Key feature of the program is its drawing engine written in C
and using directly the Xlib drawing primitives; this gives very good speed performance,
even on very big circuits. The user interface is built with the Tcl-Tk toolkit, tcl is
also the extension language used.
DOCUMENTATION AND MANUAL
http://repo.hu/projects/xschem
BUILDING & RUNNING
Please read additional information in file INSTALL_WIN for installation instructions
SUBDIRECTORIES
XSchemWin: Windows specific files (e.g. xschem.tcl, xschemrc, config.h)
INSTRUCTIONS TO ADD XSCHEM TO VISUAL STUDIO 2019
1. requirements
- Microsoft Visual Studio 2019
- Wix Toolset Visual Studio 2019 Extension (Download through Microsoft Extensions on VS 2019)
- Wix Toolset Build Tools v3.11 (Download online from wixtoolset)
- ActiveState tcl/tk 8.6 (Remember install directory where includes files are, see step h)
32-bit, 64-bit ActiveState need to match XSchem x86, x64, respectively.
- bison (Remember executabled directory for step h, preferably don't have spaces in the directory path (ie., don't use Program Files))
(http://gnuwin32.sourceforge.net/packages/bison.htm, Complete package, except sources (bison-2.4.1-setup.exe))
- flex (Remember executabled directory for step h, see bison note)
(http://gnuwin32.sourceforge.net/packages/flex.htm, Complete package, except sources (flex-2.5.4a-1.exe))
2. Create new XSchemWin project on Visual Studio 2019
a. Open VS2019
b. Create a new project
c. Select Empty Project
d. Project Name: XSchemWin
Location: D:\Projects\XSchem
Solution Name: XSchemWin (Check Place solution and project in the same directory).
e. Click Create
A new folder XSchemWin will be created (XschemWin.sln and XSchem.vcxproj)
f. Add C/H files under src into the project (e.g. svn://repo.hu/xschem/trunk/src)
- Exclude src/expandlabel.c, src/expandlabel.h, src/parselabel.c (add later after using Windows Flex and bison)
- Exclude src/xschem.tcl and src/xschemrc (add the two files from svn://repo.hu/xschem/trunk/src/XSchemWin/)
- Add config.h from svn://repo.hu/xschem/trunk/src/XSchemWin/
config.h is generated by Linux counterpart. Edit if necessary
g. XSchemWin Property Page > Linker > Input (All Configuration for x64 depending on what machine dependency you installed for Active State):
Add "tcl86t.lib;tk86t.lib" for Additional Dependencies
h. For (All Configurations, x64)
XSchemWin Property Page > VC++ Directories > Include Directories, Add "C:\ActiveTcl\include"
XSchemWin Property Page > VC++ Directories > Library Directories, Add "C:\ActiveTcl\lib"
XSchemWin Property Page > VC++ Directories > Executable Directories, Add "D:\GnuWin32\bin"
i. XSchemWin Property Page > C/C++ > Preprocessor, Add ";_CRT_SECURE_NO_WARNINGS" to proceed with the following compile error:
Severity Code Description Project File Line Suppression State
Error C4996 'sprintf': This function or variable may be unsafe. Consider using sprintf_s instead. To disable deprecation, use _CRT_SECURE_NO_WARNINGS. See online help for details. XSchemWin D:\Projects\XSchem\src\actions.c 117
j. Right click parselabel.l
Property Pages > Item type, change from "Does not participate in build" to "Custom Build Tool"
Click Apply to get options for "Custom Build tool"
Command Line: flex -l -oparselabel.c ..\src\parselabel.l
Outputs: parselabel.c
k. Right click expandlabel.y
Property Pages > Item type, change from "Does not participate in build" to "Custom Build Tool"
Command Line: bison -d -o expandlabel.c ..\src\expandlabel.y
Outputs: expandlabel.c
3. compiling
- config.h can be edited to change default's XSCHEM_LIBRARY_PATH.
It's defaulted to include the following directories:
C:/Program Files/XSchem/xschem_library/devices
C:/Program Files/XSchem/xschem_library/examples
C:/Program Files/XSchem/xschem_library/ngspice
C:/Program Files/XSchem/xschem_library/logic
C:/Program Files/XSchem/xschem_library/binto7seg
C:/Program Files/XSchem/xschem_library/pcb
C:/Program Files/XSchem/xschem_library/rom8k
Ctrl-b
- After compiling the first time, add expandlabel.c, expandlabel.h, parselabel.c into the project.
These 3 files are created in D:\Projects\XSchem\XSchemWin
4. running from Visual Studio 2019
F5

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XSchemWin/XSchemWin.sln Normal file
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Microsoft Visual Studio Solution File, Format Version 12.00
# Visual Studio Version 16
VisualStudioVersion = 16.0.29613.14
MinimumVisualStudioVersion = 10.0.40219.1
Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "XSchemWin", "XSchemWin.vcxproj", "{22C260FD-DCF7-4ED2-93AD-491F08007584}"
EndProject
Project("{930C7802-8A8C-48F9-8165-68863BCCD9DD}") = "XSchemWix", "XSchemWix\XSchemWix.wixproj", "{91FBAA21-56D3-42E7-A3E8-DF92C89CD027}"
EndProject
Global
GlobalSection(SolutionConfigurationPlatforms) = preSolution
Debug|x64 = Debug|x64
Debug|x86 = Debug|x86
Release|x64 = Release|x64
Release|x86 = Release|x86
EndGlobalSection
GlobalSection(ProjectConfigurationPlatforms) = postSolution
{22C260FD-DCF7-4ED2-93AD-491F08007584}.Debug|x64.ActiveCfg = Debug|x64
{22C260FD-DCF7-4ED2-93AD-491F08007584}.Debug|x64.Build.0 = Debug|x64
{22C260FD-DCF7-4ED2-93AD-491F08007584}.Debug|x86.ActiveCfg = Debug|Win32
{22C260FD-DCF7-4ED2-93AD-491F08007584}.Debug|x86.Build.0 = Debug|Win32
{22C260FD-DCF7-4ED2-93AD-491F08007584}.Release|x64.ActiveCfg = Release|x64
{22C260FD-DCF7-4ED2-93AD-491F08007584}.Release|x64.Build.0 = Release|x64
{22C260FD-DCF7-4ED2-93AD-491F08007584}.Release|x86.ActiveCfg = Release|Win32
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</Fragment>
</Wix>

File diff suppressed because it is too large Load Diff

30
XSchemWin/config.h Normal file
View File

@ -0,0 +1,30 @@
/*************************************************************/
/* Generated by scconfig - DO NOT EDIT - will be overwritten */
/* Source: config.h.in; to regenerate run ./configure */
/*************************************************************/
/* Define to 1 if cairo is available and is to be used */
/*#undef HAS_CAIRO */
/* Define to 1 if Xlib's xcb is available */
/*#undef HAS_XCB */
/* Define to 1 if Xlib's xrender is available */
#define HAS_XRENDER 1
/* Define to 1 if popen(3) is available */
#define HAS_POPEN 0
/* Define to 1 if popen(3) is not available but fork(2) and pipe(2) are available */
/*#undef HAS_PIPE */
#ifndef XSCHEM_LIBRARY_PATH
#define XSCHEM_LIBRARY_PATH "C:/Program Files/XSchem/xschem_library;C:/Program Files/XSchem/xschem_library/devices;C:/Program Files/XSchem/xschem_library/examples;C:/Program Files/XSchem/xschem_library/ngspice;C:/Program Files/XSchem/xschem_library/logic;C:/Program Files/XSchem/xschem_library/binto7seg;C:/Program Files/XSchem/xschem_library/pcb;C:/Program Files/XSchem/xschem_library/rom8k"
#endif
#define USER_CONF_DIR "userConf"
/* Extra includes required by the detected libs (may be empty): */
#define _XOPEN_SOURCE

49
config.h.in Normal file
View File

@ -0,0 +1,49 @@
put /tmpasm/IFS {\n}
put /local/xschem/includes [@
#define _XOPEN_SOURCE
@?libs/gui/cairo/includes@
@?libs/gui/xrender/includes@
@?libs/gui/xcb/includes@
@?libs/gui/xcb_render/includes@
@?libs/gui/xgetxcbconnection/includes@
@libs/gui/xpm/includes@
@libs/script/tk/includes@
@libs/script/tcl/includes@
@]
uniq /local/xschem/includes
put /tmpasm/IFS { \t\r\n}
print [@/*************************************************************/
/* Generated by scconfig - DO NOT EDIT - will be overwritten */
/* Source: config.h.in; to regenerate run ./configure */
/*************************************************************/@]
print {\n\n/* Define to 1 if cairo is available and is to be used */\n}
print_ternary ?libs/gui/cairo/presents {#define HAS_CAIRO 1} {/*#undef HAS_CAIRO */}
print {\n\n/* Define to 1 if Xlib's xcb is available */\n}
print_ternary ?libs/gui/xcb/presents {#define HAS_XCB 1} {/*#undef HAS_XCB */}
print {\n\n/* Define to 1 if Xlib's xrender is available */\n}
print_ternary ?libs/gui/xrender/presents {#define HAS_XRENDER 1} {/*#undef HAS_RENDER */}
print {\n\n/* Define to 1 if popen(3) is available */\n}
print_ternary ?libs/io/popen/presents {#define HAS_POPEN 1} {/*#undef HAS_POPEN */}
print {\n\n/* Define to 1 if popen(3) is not available but fork(2) and pipe(2) are available */\n}
print_ternary ?libs/io/pipe/presents {#define HAS_PIPE 1} {/*#undef HAS_PIPE */}
print [@
#define PREFIX "@/local/xschem/prefix@"
#define XSCHEM_LIBRARY_PATH "@/local/xschem/xschem-lib-path@"
#define USER_CONF_DIR "@/local/xschem/user-conf-dir@"
#define XSCHEM_SHAREDIR PREFIX "/share/xschem"
/* Extra includes required by the detected libs (may be empty): */
@/local/xschem/includes@
@]

4
configure vendored Executable file
View File

@ -0,0 +1,4 @@
#!/bin/sh
cd scconfig
make
./configure "$@"

25
doc/Makefile Normal file
View File

@ -0,0 +1,25 @@
ROOT=..
include $(ROOT)/Makefile.conf
all:
install: FORCE
$(SCCBOX) mkdir -p "$(XDOCDIR)" "$(XDOCDIR)"/xschem_man "$(MANDIR)"/man1
$(SCCBOX) install -f -d *.svg *.html *.css *.png "$(XDOCDIR)"
$(SCCBOX) install -f -d xschem_man/*.html xschem_man/*.css xschem_man/*.png "$(XDOCDIR)"/xschem_man
$(SCCBOX) install -f manpages/xschem.1 "$(MANDIR)"/man1/xschem.1
uninstall: FORCE
$(SCCBOX) rm -f "$(XDOCDIR)"/xschem_man/*
$(SCCBOX) rm -f "$(XDOCDIR)"/*
$(SCCBOX) rm -f "$(MANDIR)"/man1/xschem.1
clean:
distclean:
$(SCCBOX) rm -f manpages/xschem.1
FORCE:

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<!DOCTYPE html>
<html>
<head>
<title>xschem schematic circuit editor - VHDL Verilog Spice
netlister</title>
<meta content="stefan.schippers@gmail.com" name="author">
<meta content="EDA tool for drawing hierarchical circuit schematics
and making Spice - Verilog - VHDL netlists for simulation"
name="description">
<link rel="stylesheet" type="text/css" href="style.css" />
<style type="text/css">
h2 {
text-shadow: 10px 10px 9px #aa4;
}
.just { text-align: justify; }
</style>
</head>
<body>
<iframe class="menu_iframe" seamless src="menu_xschem.html"> </iframe>
<div class="body1">
<div
style="background:url(xschem.png);background-size: 100% 150px;
width:100%; height: 150px;"
>
<h1><br>
XSCHEM : schematic capture<br>and netlisting EDA tool
</h1>
</div>
<br>
<p class='just'>
<b>Xschem</b> is a schematic capture program, it allows creation of
hierarchical representation of circuits with a top down approach .
By focusing on interfaces, hierarchy and instance properties a
complex system can be described in terms of simpler building blocks.
A VHDL or Verilog or Spice netlist can be generated from
the drawn schematic, allowing
the simulation of the circuit. Key feature of the program is its
drawing engine written in C and using directly the Xlib drawing
primitives; this gives very good speed performance, even on very
big circuits. The user interface is built with the Tcl-Tk toolkit,
tcl is also the extension language used.<br></p>
<h2 style="text-align: center;">Features</h2>
<ul>
<li>hierarchical schematic drawings, no limits on size</li>
<li>any object in the schematic can have any sort of properties
(generics in VHDL, parameters in Spice or Verilog)<br>
</li>
<li>new Spice/Verilog primitives can be created, and the netlist
format can be defined by the user</li>
<li>tcl extension language allows the creation of scripts; any
user command in the drawing window has an associated tcl comand</li>
<li>VHDL / Verilog / Spice netlist, ready for simulation</li>
<li>Behavioral VHDL / Verilog code can be embedded as one of the
properties of the schematic block, <br>
</li>
</ul>
<br>
Xschem runs on UNIX systems with X11 and Tcl-Tk toolkit installed.<br>
<br>
<h2 style="text-align: center;">Documentation</h2>
<div style="text-align: center;">
<a href="xschem_man/xschem_man.html" target="_blank">XSCHEM manual</a>
<br>
<a href="xschem_man/XSCHEM_2.9.2_Manual_Tutorials.pdf" target="_blank">XSCHEM PDF manual</a>
</div>
<h2 style="text-align: center;">Download</h2>
<div style="text-align: center;">
<a href="releases/">Current release</a>
<br>
<a href="https://sourceforge.net/projects/xschem/" target="_blank">Old XSCHEM releases on Sourceforge</a>
<br>
SVN: svn checkout svn://repo.hu/xschem/trunk<br>
<br>
</div>
<h2 style="text-align: center;">License</h2>
<div style="text-align: center;">The software is released under
the GNU GPL, General Public License<br>
<br>
<h2>Contact</h2>
Anyone interested in this project please contact me at the
following address:<br>
<h4>STEFAN.SCHIPPERS@GMAIL.COM</h4><br>
<br>
</div>
<h2 style="text-align: center;">Software requirements:</h2>
- X11<br>
- tcl-tk libs and developent files<br>
- c99 compiler<br>
- bison (only for compiling the grammar parser)<br>
- flex (only for compiling the lexical analyzer<br>
- Xpm library and -dev header files<br>
- awk (tested with gawk and mawk)<br>
<div style="text-align: center;">
<h2>Systems tested:</h2>
</div>
- Linux debian / Redhat<br>
- Solaris sparc<br>
- Windows (with the cygwin layer and cygwin/Xorg X11 server,
plus the tcl/tk toolkit and the -dev libraries) <br>
<br>
<br>
<div style="text-align: center;"><br>
</div>
<h2 style="text-align: center;">Screenshots<br>
</h2>
<div style="text-align: center;">
<div style="text-align: left;">
<ul>
<li>analog circuit example<br>
</li>
</ul>
</div>
<br>
<img style=" border:5px solid #996622 ; box-shadow: 10px 10px 9px #aa4;"
alt="analog circuit
example" title="analog circuit example" src="xschem1.png"><br>
<br>
<div style="text-align: left;">
<ul>
<li>digital system for VHDL simulation<br>
</li>
</ul>
</div>
<br>
<img style=" border:5px solid #996622;box-shadow: 10px 10px 9px #aa4;"
alt="dicital example"
title="digital example" src="xschem2.png"><br>
</div>
<br>
</div>
</body>
</html>

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print [@
.\" xschem - manual
.\" Copyright (C) 2018 Tibor 'Igor2' Palinkas
.\"
.\" This program is free software; you can redistribute it and/or modify
.\" it under the terms of the GNU General Public License as published by
.\" the Free Software Foundation; either version 2 of the License, or
.\" (at your option) any later version.
.\"
.\" This program is distributed in the hope that it will be useful,
.\" but WITHOUT ANY WARRANTY; without even the implied warranty of
.\" MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
.\" GNU General Public License for more details.
.\"
.\" You should have received a copy of the GNU General Public License along
.\" with this program; if not, write to the Free Software Foundation, Inc.,
.\" 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
.\"
.\" Contact: TODO: an email address
.TH xschem 1 2018-01-01 "" "xschem manual"
.SH NAME
xschem - schematic capture and netlisting EDA tool
.SH SYNPOSIS
.nf
.sp
\fBxschem [\fIoptions\fB] [\fIinputfile\fB]
.fi
.SH DECSRIPTION
.BR Xschem
is a schematic capture program, it allows creation of
hierarchical representation of circuits with a top down approach.
.SH OPTIONS
.TP
.B -h, --help
Print help and exit.
.TP
.B -n, --netlist
Do a netlist of the given schematic cell.
.TP
.B -v, --version
Print version information and exit.
.TP
.B -V, --vhdl
Set netlist type to VHDL.
.TP
.B -S, --simulate
Run a simulation of the current schematc file (spice/Verilog/VHDL, depending on the netlist type chosen).
.TP
.B -w, --verilog
Set netlist type to Verilog.
.TP
.B -i, --no_rcload
Do not load any xschemrc file.
.TP
.B -o, --netlist_path
Set output for netlist.
.TP
.B -t, --tedax
Set netlist type to tEDAx.
.TP
.B -s, --spice
Set netlist type to SPICE.
.TP
.B -3, --a3page
Set page size for pdf export to A3.
.TP
.B -x, --no_x
Dont use X (only command mode).
.TP
.B --events
Do not use tclreadline, empty tcl shell prompt, dump activity on stdout for remote controlling other software.
.TP
.B -z, --rainbow
Use a raibow-looking layer color table.
.TP
.B -W, --waves
Show simulation waveforms.
.TP
.B -f, --flat_netlist
Set flat netlist (for spice format only).
.TP
.B -r, --no_readline
Start without the tclreadline package ( this is necessary if stdin and stdout are to be redirected for example to /dev/null).
.TP
.B -c, --color_ps
Set color postscript.
.TP
.B --plotfile <file>
Use <file> as output for plot export (png, svg, postscript/pdf)
.TP
.B --rcfile <file>
Use <file> as a rc file for startup instead of the default xschemrc.
.TP
.B --tcl <tcl command>
Execute specified tcl instructions before any other action, this can be used to change xschemrc variables.
.TP
.B --script <tcl file>
Execute specified tcl file as a command script, perhaps with xschem commands.
.TP
.B -p, --postscript, --pdf
Export pdf schematic.
.TP
.B --png
Export png schematic.
.TP
.B --svg
Export svg schematic.
.TP
.B -q, --quit
Quit after doing things (no interactive mode).
.TP
.B -l file, --log file
Set a log file.
.TP
.B -d n, --debug n
Set debug level: 1, 2, 3,...: C program debug, -1, -2, -3...: TCL frontend debug.
.SH FILES
.TP
.B @/local/xschem/prefix@/share/xschem/xschemrc
default configuration.
.TP
.B ~/.xschem/xschemrc
user configuration; if exists overrides settings from default configuration;
may be partial: settings not overridden will remain as set from the system
config.
.TP
.B ./xschemrc
local/per-project configuration; if exists overrides settings from
the user configuration and default configuration.
.TP
.B @/local/xschem/prefix@/share/xschem/systemlib
builtin essentials, such as font and missing symbol graphics.
.TP
.B @/local/xschem/prefix@/share/xschem/utile
TODO.
.TP
@]

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<!DOCTYPE html>
<html>
<head>
<link rel="stylesheet" type="text/css" href="style.css" />
</head>
<body class="menu">
<p class="menu">
<a class="menu_a" href="xschem_man/xschem_man.html" target="_parent" >XSCHEM MANUAL</a>
</p>
</body>
</html>

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<!DOCTYPE html>
<html>
<head>
<title>SYMBOLS</title>
<link rel="stylesheet" type="text/css" href="xschem_man.css" />
<style type="text/css">
/* Local styling goes here */
p{padding: 15px 30px 10px;}
</style>
</head>
<body>
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<!-- slide title -->
<h1>SYMBOLS</h1><br>
<p>
The best way to understand how a symbol is defined is to analyze an existing one.
Load a test schematic (for example <kbd>test.sch</kbd>). Let's consider the
resistor symbol. Use the <kbd>Insert</kbd> key to place the <kbd>devices/res.sym</kbd> symbol.
</p>
<img src="xschem_insert.png">
<p>
Use the file selector dialog to locate <kbd>res.sym</kbd>.
</p>
<img src="building_symbol_01.png">
<p>
Now select the resistor by left-clicking on it (it will turn to grey color)
</p>
<img src="building_symbol_02.png">
<p>
After selecting the component (component is an instance of a symbol)
descend into its symbol definition
by pressing the <kbd>'i'</kbd> key. XSCHEM will load the
<kbd>devices/res.sym</kbd> file and show it in
the drawing window. Before descending it asks if you want to save
the parent schematic drawing
before loading the resistor symbol. Answer 'yes'.
</p>
<img src="building_symbol_03.png">
<p>
The image above is the 'symbol definition', you can now select individual graphic elements that
represent the symbol, lines, rectangles and text.
Normally a symbol contains some pins, these are just rectangles drawn on the 'pin' layer, and some
graphics / descriptive text. Another fundamental part of symbols are properties.
Properties are text strings that define attributes of the symbol, for example:
</p>
<ul>
<li>The name of the connection pins</li>
<li>The type of the symbol (spice primitive, subcircuit, documentation)</li>
<li>The format of the spice/verilog/VHDL netlist for the symbol</li>
</ul>
<p>
We will return on symbols after explaining properties.
</p>
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<!DOCTYPE html>
<html>
<head>
<title>EDITOR COMMANDS</title>
<link rel="stylesheet" type="text/css" href="xschem_man.css" />
<style type="text/css">
/* Local styling goes here */
p{padding: 15px 30px 10px;}
</style>
</head>
<body>
<!-- start of slide -->
<div class="content">
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<a href="netlisting.html" class="next">NEXT</a>
<!-- slide title -->
<h1>EDITOR COMMANDS</h1><br>
<p>
Most editing commands are available in the menu, but definitely key-bindings and Mouse actions
are the most effective way to build and arrange schematics, so you should learn at least the
most important ones.
</p>
<p>
The basic principle in XSCHEM is that first you select something in the circuit then you
decide what to do with the selection.
For example, if you need to change an object property you first select it (mouse click) and then
you press the edit property (<kbd>'q'</kbd>) key.
It you need to move together multiple objects you select them (by area or using multiple mouse
clicks with the <kbd>Shift</kbd> key), then you press the move (<kbd>'m'</kbd>) key.
</p>
<h3> EDITOR COMMAND CHEATSHEET</h3>
<p>
This list is available in XSCHEM in the <kbd>Help</kbd> menu
</p>
<pre class="code" style="height: 600px;">
XSCHEM MOUSE BINDINGS
----------------------------------------------------------------------
LeftButton Clear selection and select a graphic object
(line, rectangle, symbol, wire)
if clicking on blank area: clear selection
shift + LeftButton Select without clearing previous selection
ctrl + LeftButton if an 'url' or 'tclcommand' property is defined on
selected instance open the url or execute the
tclcommand
LeftButton drag Select objects by area, clearing previous selection
shift + LeftButton drag Select objects by area, without clearing
previous selection
Ctrl + LeftButton drag Select objects by area to perform a
subsequent 'stretch' move operation
Shift + Select objects by area without unselecting
Ctrl + LeftButton drag to perform a subsequent 'stretch' move operation
Mouse Wheel Zoom in / out
MidButton drag Pan viewable area
Alt + LeftButton Unselect selected object
Alt + LeftButton drag
Unselect objects by area
RightButton Edit property of object under the mouse
else edit global schematic / symbol property string
Shift + RightButton Edit property of object under the mouse
else edit global schematic / symbol property string
using the specified (or default) text editor.
LeftButton Double click Terminate Polygon placement
XSCHEM KEY BINDINGS
----------------------------------------------------------------------
- BackSpace Back to parent schematic
- Delete Delete selected objects
- Insert Insert element from library
- Down Move down
ctrl Enter Confirm closing dialog boxes
- Escape Abort, redraw, unselect
- Left Move right
- Right Move left
- Up Move up
- '!' Break selected wires at any wire or component pin
connection
- ' ' Pan schematic
- ' ' When drawing lines or wires toggle between
manhattan H-V, manhattan V-H or oblique path.
- '#' Highlight components with duplicated name (refdes)
ctrl '#' Rename components with duplicated name (refdes)
- '5' View only probes
- 'a' Make symbol from pin list of current schematic
ctrl 'a' Select all
shift 'A' Toggle show netlist
- 'b' Merge file
ctrl 'b' Toggle show text in symbol
- 'c' Copy selected obj.
ctrl 'c' Save to clipboard
shift 'C' Start arc placement
shift+ctrl 'C' Start circle placement
alt 'C' Toggle dim/brite background with rest of layers
ctrl 'e' Back to parent schematic
- 'e' Descend to schematic
alt 'e' Edit selected schematic in a new window
'\' Toggle Full screen
shift 'F' Flip
alt 'f' Flip objects around their anchor points
ctrl 'f' Find/select by substring or regexp
- 'f' Full zoom
shift 'G' Double snap factor
- 'g' Half snap factor
ctrl 'g' Set snap factor
alt 'g' Hilight selected nets and send to gaw waveform viewer
- 'h' Constrained horizontal move/copy of objects
alt 'h' create symbol pins from schematic pins
ctrl 'h' Follow http link or execute command (url, tclcommand properties)
shift 'H' Attach net labels to selected instance
- 'i' Descend to symbol
alt 'i' Edit selected symbol in a new window
shift 'J' Create symbol from pin list
alt+shift 'J' Create labels with 'i' prefix from highlighted nets/pins
alt 'j' Create labels without 'i' prefix from highlighted nets/pins
ctrl 'j' Create ports from highlight nets
alt+ctrl 'j' Print list of highlighted nets/pins with label expansion
- 'j' Print list of highlighted nets/pins
shift 'J' create xplot plot file for ngspice in simulation directory
(just type xplot in ngspice)
- 'k' Hilight selected nets
ctrl+shift 'K' highlight net passing through elements with 'propagate_to' property set on pins
shift 'K' Unhilight all nets
ctrl 'k' Unhilight selected nets
- 'l' Start line
ctrl 'l' Make schematic view from selected symbol
alt 'l' add lab_pin.sym to schematic
alt+shift 'l' add lab_wire.sym to schematic
ctrl 'o' Load schematic
- 'm' Move selected obj.
shift 'N' Hierarchical netlist
- 'n' Netlist
ctrl 'n' New schematic
ctrl+shift 'N' New symbol
shift 'O' Toggle Light / Dark colorscheme
ctrl 'o' Load schematic
alt 'p' Add symbol pin
ctrl 'p' Pan schematic view
shift 'P' Pan, other way to.
alt 'q' Edit schematic file (dangerous!)
- 'q' Edit prop
shift 'Q' Edit prop with vim
ctrl+shift 'Q' View prop
ctrl 'q' Exit XSCHEM
alt 'r' Rotate objects around their anchor points
shift 'R' Rotate
- 'r' Start rect
shift 'S' Change element order
ctrl+shift 'S' Save as schematic
ctrl 's' Save schematic
alt 's' Reload current schematic from disk
ctrl+alt 's' Save-as symbol
- 't' Place text
alt 'u' Align to current grid selected objects
shift 'U' Redo
- 'u' Undo
- 'v' Constrained vertical move/copy of objects
ctrl 'v' Paste from clipboard
shift 'V' Toggle spice/vhdl/verilog netlist
- 'w' Place wire
ctrl 'w' Place polygon. Operation ends by placing last point over first.
shift 'W' Place wire, snapping to closest pin or net endpoint
ctrl 'x' Cut into clipboard
- 'x' New cad session
shift 'X' Highlight discrepancies between object ports and attached nets
- 'y' Toggle stretching wires
- 'z' Zoom box
shift 'Z' Zoom in
ctrl 'z' Zoom out
- '?' Help
- '&amp;' Join / break / collapse wires
shift '*' Postscript/pdf print
ctr+shift '*' Xpm/png print
alt+shift '*' Svg print
'-' dim colors
ctrl '-' Test mode: change line width
ctrl '+' Test mode: change line width
'+' brite colors
- '_' Toggle change line width
- '%' Toggle draw grid
- '=' Toggle fill rectangles
- '$' Toggle pixmap saving
ctrl '$' Toggle use XCopyArea vs drawing primitives for drawing the screen
- ':' Toggle flat netlist
</pre><br>
<h3>KEYBIND CUSTOMIZATION</h3>
<p>
changes to default keybindings may be placed in the <kbd>~/.xschem</kbd> file as in the following examples:
</p>
<pre class="code">
## replace Ctrl-d with Escape (so you won't kill the program :-))
set replace_key(Control-d) Escape
## swap w and W keybinds; Always specify Shift for capital letters
set replace_key(Shift-W) w
set replace_key(w) Shift-W
</pre><br>
<h3>STRETCH OPERATIONS</h3>
<p>
An important operation that deserves a special paragraph is the <kbd>Stretch</kbd> operation.
There is frequently the need to move part of the circuit without breaking connections, for
example to create more room for other circuitry or just to make it look better.
The first thing to do is to drag a selection rectangle with the mouse holding down the
<kbd>Ctrl</kbd> key, cutting wires we need to stretch:
</p>
<img src="commands1.png">
<p>
After selection is done hit the move (<kbd>'m'</kbd>) key. You will be able to move the selected part
of the schematic keeping connected the wires crossing the selection rectangle:
</p>
<img src="commands2.png">
<p>
In our example we needed to move up part of the circuit, the end result is shown in next picture.
Multiple stretch rectangles can be set using the <kbd>Shift</kbd> key in addition to the
<kbd>Ctrl</kbd> key after setting the first stretch area.
</p>
<img src="commands3.png">
<h3>PLACE WIRES SNAPPING TO CLOSEST PIN OT NET ENDPOINT</h3>
<p>
The (uppercase) <kbd>'W'</kbd> bindkey allows to place a wire putting start (and end point, later) to the
closest pin or wire endpoint, this will make it easier to connect precisely without the need to zoom in all times.
</p><br>
<h3>CONSTRAINED MOVE</h3>
<p>
while creating wires, lines, and moving, stretching, copying objects, pressing the <kbd>'h'</kbd> or <kbd>'v'</kbd> keys
will constrain the movement to a horizontal or vertical direction, respectively.
</p>
<img src="commands4.png" style="margin-bottom: 0px;" >
<p style="padding-top:0px;"> <i>
Constrained horizontal move: regardless of the mouse pointer Y position movement
occurs on the X direction only.
</i></p>
<img src="commands5.png" style="margin-bottom: 0px;">
<p style="padding-top:0px;"> <i>
Unconstrained move: objects follow the mouse pointer in X and Y direction.
</i></p>
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<!DOCTYPE html>
<html>
<head>
<title>COMPONENT INSTANTIATION</title>
<link rel="stylesheet" type="text/css" href="xschem_man.css" />
<style type="text/css">
/* Local styling goes here */
p{padding: 15px 30px 10px;}
</style>
</head>
<body>
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<!-- slide title -->
<h1>COMPONENT INSTANTIATION</h1><br>
<p>
In the <a href="run_xschem.html">RUN XSCHEM</a> slide some instructions were provided as examples to
place a component in the schematic. Now we will cover the topic in more detail with emphasis on
component properties. Start by opening a test schematic window (you may delete any existing
stuff in it if any).
</p>
<img src="load_schematic.png">
<p>
Now start by inserting a component, consider for example <kbd>devices/nmos4.sym</kbd>; press the
<kbd>Insert</kbd> key, navigate to the <kbd>devices</kbd> design library and open the <kbd>nmos4.sym</kbd>
symbol.
</p>
<img src="nmos4_symbol.png">
<p>
Now draw some wires on each pin of the nmos; place the mouse pointer on the component pins and
use the <kbd>'w'</kbd> bindkey.
</p>
<img src="nmos4_wires.png">
<p>
we need now to put labels on wire ends: use the <kbd>Insert</kbd> key and locate the
<kbd>devices/lab_pin.sym</kbd> symbol. After the <kbd>lab_pin</kbd> symbol is placed you can move it
by selecting it with the mouse and pressing the <kbd>'m'</kbd> bindkey. You can also flip
( <kbd>'F'</kbd>) and rotate while moving (<kbd>'R'</kbd>) to adjust the orientation. After
placing the first one you may copy the others from it (<kbd>'c'</kbd> bindkey). The end result
should look like this:
</p>
<img src="nmos4_labels.png">
<p>
This is what an electrical circuit is all about: a network of wires and components. In this
schematic we have 5 components (4 labels and one mos) and 4 nets. It is not mandatory to put a
wire segment between component pins; we could equally well do this:
</p>
<img src="nmos4_labels2.png">
<p>
This circuit is absolutely equivalent to the previous one: it will produce the same
device connectivity netlist.<br>
Now we need to set appropriate labels on the NMOS terminals. This is -again- accomplished with
component properties. Select the wire label on the nmos source pin and press the <kbd>'q'</kbd>
bindkey:
</p>
<img src="nmos4_editprop.png">
<p>
Now, replace the 'xxx' default string in the dialog with a different name (example: SOURCE)
After clicking <kbd>OK</kbd> the source terminal will have the right label.
</p>
<img src="nmos4_editprop2.png">
<p>
repeat the process for the remaining GATE, DRAIN, BODY terminals;
</p>
<img src="nmos4_editprop3.png">
<p>
The following picture shows the <kbd>lab_pin</kbd> component with its properties and
the corresponding symbol definition with its global properties (remember global properties in
the <a href="xschem_properties.html">xschem_properties</a> slide)
</p>
<img src="properties.png" style="height:70%;">
<p>
when building the netlist XSCHEM will look for wires that touch the red square of the lab_pin
component and name that wires with the component 'lab' property.
for example the SPICE netlist of the circuit will be:
<pre class="code">m1 DRAIN GATE SOURCE BODY nmos w=5u l=0.18u m=1</pre>
</p>
<p>
We need now to edit the nmos properties. Select it and press the <kbd>'q'</kbd> bindkey
</p>
<img src="nmos_properties.png">
<p>
from the edit properties dialog you see there are 5 attributes with values defined:
</p>
<ul>
<li> The component name <kbd>name=m1</kbd>.</li>
<li> The spice model to be used in simulation <kbd>model=nmos</kbd>.</li>
<li> The transistor width <kbd>w=5u</kbd>.</li>
<li> The transistor channel length <kbd>l=0.18u</kbd>.</li>
<li> The number of parallel transistors (multiplicity) <kbd>m=1</kbd>.</li>
</ul>
<p>
We have never defined a value for these properties. These are the default values defined in the
<kbd>template</kbd> attribute in the global <kbd>nmos4.sym</kbd> property string.
</p>
<img src="nmos_properties2.png">
<p>
We may want to change the dimensions of the transistor; simply change the <kbd>w</kbd> and
<kbd>l</kbd> attribute values.<br>
Also the component name may be changed as long as it is unique in the current schematic window.
All simulators require that components are unique, it is not permitted to have 2 components
with identical name, so XSCHEM enforces this.
</p>
<img src="nmos_properties3.png">
<p>
If a name is set that matches an existing component
xschem will rename it keeping the first letter (<kbd>m</kbd> in this example) and appending a number
(so you might end up in something like <kbd>m23</kbd> if there are many devices).
</p>
<p class="important">
the <kbd>name</kbd> attribute is unique in the schematic window, and must be placed first in the
property string. The name is also used by xschem to efficiently index it in the internal
hash tables.
</p><br>
<h3>SPECIAL COMPONENTS</h3>
<p>General purpose</p>
<ul>
<li><kbd>devices/ipin.sym</kbd></li>
<li><kbd>devices/opin.sym</kbd></li>
<li><kbd>devices/iopin.sym</kbd></li>
<p>
These components are used to name a net or a pin of another component. They do not have any other function
other than giving an explicit name to a net.
</p>
<img src="special1.png">
<li><kbd>devices/lab_pin.sym</kbd></li>
<li><kbd>devices/lab_wire.sym</kbd></li>
<li><kbd>devices/launcher.sym</kbd></li>
<li><kbd>devices/architecture.sym</kbd><p> This prints global attributes of the schematic. Attributes of this
symbol should not be set. It is a readonly symbol printing top-level schematic properties.</p></li>
</ul>
<p>Spice netlist special components</p>
<ul>
<li><kbd>devices/code.sym</kbd></li>
<li><kbd>devices/code_shown.sym</kbd></li>
<p> these symbols are used to place simulator commands or additional netlist lines as text into the schematic.</p>
</ul>
<p>Verilog netlist special components</p>
<ul>
<li><kbd>devices/verilog_timescale.sym</kbd></li>
<li><kbd>devices/verilog_preprocessor.sym</kbd></li>
</ul>
<p>VHDL netlist special components</p>
<ul>
<li><kbd>devices/use.sym</kbd></li>
<li><kbd>devices/package.sym</kbd></li>
<li><kbd>devices/package_not_shown.sym</kbd></li>
<li><kbd>devices/arch_declarations.sym</kbd></li>
<li><kbd>devices/attributes.sym</kbd></li>
<li><kbd>devices/port_attributes.sym</kbd></li>
<li><kbd>devices/generic_pin.sym</kbd></li>
<li><kbd>devices/generic.sym</kbd></li>
</ul><br>
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<!DOCTYPE html>
<html>
<head>
<title>COMPONENT PROPERTY SYNTAX</title>
<link rel="stylesheet" type="text/css" href="xschem_man.css" />
<style type="text/css">
/* Local styling goes here */
p{padding: 15px 30px 10px;}
</style>
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<!-- slide title -->
<h1>COMPONENT PROPERTY SYNTAX</h1><br>
<p>
Component property strings can be set in the usual way with the <kbd>'q'</kbd> on a selected
component instance or by menu <kbd>Properties&nbsp;--&gt;&nbsp;Edit</kbd>
</p>
<img src="component_properties.png">
<p>
The dialog box allows to change the property string as well as the symbol reference. The property string
is essentially a list of <kbd>attribute=value</kbd> items. As with symbol properties if a <kbd>value</kbd>
has white space it should be double-quoted.
The following property definitions are identical:
</p>
<pre class=code>
name=mchanged_name model=nmos w=20u l=3u m=10
</pre><br>
<pre class=code>
name="mchanged_name" model="nmos" w="20u" l="3u" m="10"
</pre><br>
<p>
Given the role of the <kbd>"</kbd> character, if quoted values are needed escapes must be used, like in
the following example where the model name will be with quotes in netlist:
</p>
<pre class=code>
name="mchanged_name" model="\"nmos\"" w="20u" l="3u" m="10"
</pre>
<p>or</p>
<pre class=code>
name="mchanged_name" model=\"nmos\" w="20u" l="3u" m="10"
</pre>
<p>
the resulting SPICE netlist will be:<br>
<kbd>mchanged_name DRAIN GATE SOURCE BODY "nmos" w=20u l=3u m=10</kbd>
</p>
<p>
There is no limit on the number of <kbd>attribute=value</kbd> items, each attribute should have a corresponding
<kbd>@attribute</kbd> in the symbol definition format, but this is not a requirement. There are a number
of special attributes as we will see later.
</p>
<p class="important">
Important: a <kbd>name=&lt;inst_name&gt;</kbd> item is mandatory and must be placed
in component property string to get a valid netlist, as this is the partname or so-called refdes (reference designator).
If <kbd>&lt;inst_name&gt;</kbd> is already used in another component XSCHEM will
auto-rename it to a unique name preserving the first letter (which ts a device type indicator
for SPICE like netlists).
</p>
<h3>PREDEFINED COMPONENT ATTRIBUTES</h3>
<ul>
<li><kbd>name</kbd></li>
<p> This defines the name of the instance.
Names are unique, so if for example multiple MOS components are
placed in the design one should be named <kbd>m1</kbd> and the second <kbd>m2</kbd> or anything
else, provided the names are different. XSCHEM enforces this,
unless <kbd>Options -&gt; allow duplicated instance names</kbd> is set. If a name is given that already
exist in the current schematic it will be renamed. Normally the template string defines a default
name for a given component, and expecially for SPICE compatibility, the first character must NOT
be changed. For example, the default name for a MOS transistor is <kbd>m1</kbd>, it can be renamed
for example to <kbd>mcurr_source</kbd> but not for example to <kbd>dcurr_source</kbd>. XSCHEM
does not enforce that the first character is preserved, it's up to the designer to keep it
consistent with the component type.</p>
<li><kbd>embed</kbd></li>
<p>
When the <kbd>embed=true</kbd> is set on a component instance
the corresponding symbol will be saved into the schematic (.sch) file on the next save operation.
This allows to distribute schematic files that contain the used symbols so these
will not depend on external library symbols.
When this attribute is set on a component instance, all instances in the schematic referring to the same
symbol will use the embedded symbol definition.
When descending into an embedded symbol, any changes will be local, meaning that no library symbol
will be affected. The changes will be saved using the embedded tag (<kbd>[...]</kbd>) into the
schematic file.
Removing this attribute will revert to external symbols after saving and reloading the schematic file.
</p>
<li><kbd>url</kbd></li>
<p> This attribute defines a location (web page, file) that can be viewed when hitting the
<kbd>&lt;shift&gt;H</kbd> key (or <kbd>&lt;Alt&gt; left mouse buttoni</kbd>) on a selected component.
This is very useful to link a datasheet to a
component, for example. The default program used to open the url is <kbd>xdg-open</kbd>.
this can be changed in the <kbd>~/xschemrc</kbd> configuration file with the <kbd>launcher_default_program</kbd>
variable.
<kbd>url</kbd> can be an http link or a local file that has a default association known to xdg-open.</p>
<li><kbd>program</kbd></li>
<p> this attribute can be used to specify an application to be used to open the <kbd>url</kbd> link,
if the default application has to be changed or the file type is unknown.
for example <kbd>program=evince</kbd> may be given to specify an application for a pdf file
specified with <kbd>url</kbd></p>
<li><kbd>tclcommand</kbd></li>
<p> this can be any tcl statement (or group of statements separated by semicolons) including all xschem-specific
commands, the statement will be executed when pressing the <kbd>&lt;shift&gt;H</kbd> key
(or <kbd>&lt;Alt&gt; left mouse button</kbd>) on the selected instance.
<br>The <kbd>tclcommand</kbd> and <kbd>url</kbd> properties are mutually exclusive.</p>
<img src="component_properties3.png">
<li><kbd>only_toplevel</kbd></li>
<p>this attribute is valid only on <kbd>netlist_commands</kbd> type symbols and specifies that the
symbol should be netlisted only if it is instantiated in the top-most hierarchy. This is very usefull
for spice commands. Spice commands are placed in a special <kbd>netlist</kbd> component as we will see
and are meaningfull only when simulating the block, but should be skipped if the component
is simulated as part of a bigger system which has its own (at higher hierarchy level)
<kbd>netlist</kbd>component for Spice commands.</p>
<img src="component_properties0.png">
<li><kbd>lock</kbd></li>
<p> A <kbd>lock=true</kbd> attribute will make the symbol not editable. the only way to make it editable again is
to right click on it to bring up the edit attributes dialog box and set to false. This is useful for title
symbols. </p>
<li><kbd>place</kbd></li>
<p> This
<kbd>place=end</kbd> attribute is only valid only for <kbd>netlist_commands</kbd> type symbols, and tells
XSCHEM that this component must be netlisted last. This is necessary for some spice commands
that need to be placed <b>after</b> the rest of the netlist.</p>
<li><kbd>spice_ignore</kbd></li>
<p> This tells XSCHEM that for SPICE netlist this component will be <b>completely</b> ignored.</p>
<li><kbd>verilog_ignore</kbd></li>
<p> This tells XSCHEM that for Verilog netlist this component will be <b>completely</b> ignored.</p>
<li><kbd>vhdl_ignore</kbd></li>
<p> This tells XSCHEM that for VHDL netlist this component will be <b>completely</b> ignored.</p>
<li><kbd>sig_type</kbd></li>
<p> For VHDL type netlist, this tells that the current label names a signal (or constant) of
type <kbd>sig_type</kbd>. For example a label can be placed with name <kbd>TEST</kbd> and
<kbd>sig_type=BIT</kbd>. The default type for VHDL if this property is missing is <kbd>std_logic</kbd>.
The following picture shows the usage of <kbd>sig_type</kbd> and the resulting VHDL netlist.
This property is applicable only to <kbd>label</kbd> type components: <kbd>ipin.sym</kbd>,
<kbd>iopin.sym</kbd>, <kbd>opin.sym</kbd>, <kbd>lab_pin.sym</kbd>, <kbd>lab_wire.sym</kbd>.
</p>
<img src="component_properties1.png">
<li><kbd>verilog_type</kbd></li>
<p>This is the same as sig_type but for verilog netlisting: can be used to declare a <kbd>wire</kbd>
or a <kbd>reg</kbd> or any other datatype supported by the verilog language.
</p>
<li><kbd>generic_type</kbd></li>
<p><kbd>generic_type</kbd> defines the type of parameters passed to VHDL components.
Consider the following examples of placement of <kbd>generic_pin</kbd> components in a
VHDL design:
</p>
<img src="component_properties2.png">
<p> As you will see in the <a href="parameters.html">parameters</a> slide, generics (they are just
parameters passed to components) can be passed also via property strings in addition to using
<kbd>generic_pin</kbd> components.</p>
<li><kbd>class</kbd></li>
<p>The <kbd>class</kbd> attribute is used to declare the class of a VHDL signal, most used classes are
<kbd>signal</kbd> and <kbd>constant</kbd>. Default if missing is <kbd>signal</kbd>.</p>
<li><kbd>device_model</kbd></li>
<p>
This attribute contains a SPICE .model or .subckt specification (<kbd>device_model=".model D1N4148 D ...."</kbd>)
that will be printed at end of netlist only once for the specified component (D1N4148 in the example).
<kbd>device_model</kbd> attributes defined at instance level override the <kbd>device_model</kbd> set
in the symbol if any.
</p>
<li><kbd>pinnumber(name)</kbd></li>
<p> This will override at instance level the value of attribute <kbd>pinnumber</kbd> of pin <kbd>name</kbd> of the symbol.
This is mainly used for tedax, where by back annotation a connection to a symbol must be changed.</p>
<li><kbd>pinnumber(index)</kbd></li>
<p> This will override at instance level the value of attribute <kbd>pinnumber</kbd> of <kbd>index</kbd>th pin of the symbol.
This is mainly used for tedax, where by back annotation a connection to a symbol must be changed.
This notation is faster since xschem does not have to find a pin by string matching.</p>
</ul><br>
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<title>CREATING A CIRCUIT SCHEMATIC</title>
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<h1>CREATING A CIRCUIT SCHEMATIC</h1><br>
<p>
To create a new circuit start from an empty window, run xschem and select <kbd>New Schematic</kbd>
in the <kbd>File</kbd> menu.
Suppose we want co create a NAND gate, with two inputs, A and B and one output, Z.
Lets start placing the input and output schematic pins; use the <kbd>Insert</kbd> key and locate the
<kbd>devices/ipin.sym</kbd> symbol. After placing it change its lab attribute to <kbd>'A'</kbd>
</p>
<img src="creating_schematic1.png">
<p>
Copy another instance of it and set its lab attribute to <kbd>B</kbd>. Next place an output pin
<kbd>devices/opin.sym</kbd> and set its lab to <kbd>Z</kbd>. The result will be as follows:
</p>
<img src="creating_schematic2.png">
<p>
Now we need to build the actual circuit. Since we plan to do it in CMOS technology we need
nmos and pmos transistors. Place one nmos from <kbd>devices/nmos4.sym</kbd> and one
pmos from <kbd>devices/pmos4.sym</kbd> By selecting them with the mouse, moving (<kbd>m</kbd> bindkey),
copying (<kbd>'c'</kbd> bindkey) place 4 transistors in the following way (the upper ones are pmos4,
the lower ones nmos4):
</p>
<img src="creating_schematic3.png">
<p>
now draw wires to connect together the transistor to form a NAND gate; in the picture i have highlighted
2 electrical nodes by selecting one wire segment of each and pressing the <kbd>'k'</kbd> bindkey.
</p>
<img src="creating_schematic4.png">
<p>
Next we need to place the supply nodes , VCC and VSS. we decide to use global nodes. Global nodes in
SPICE semantics are like global variables in C programs, they are available everywhere, we do not
need to propagate global nodes with pins. We could equally well use regular pins , as used for the
A and B inputs, I am just showing different design styles.
Use the <kbd>Insert</kbd> key and place both <kbd>devices/vdd.sym</kbd> and <kbd>devices/gnd.sym</kbd>
Since the default names are respectively VDD and GND use the edit property bindkey <kbd>'q'</kbd>
to change these to VCC and VSS.
</p>
<img src="creating_schematic5.png">
<p>
we still need to connect the body terminals of the mos transistors. One possibility is to
hookup the two upper pmos transistor terminals to VCC with wires, and the two bottom nmos
terminals to VSS with wires, but just to show different design styles i am planning to use
''by name'' connection with labels. So place a wire label <kbd>devices/lab_pin.sym</kbd> and
use 4 instances of it to name the 4 body terminals. Remember, while moving (select and press
the <kbd>'m'</kbd> key) you can flip/rotate using the <kbd>R</kbd>/<kbd>F</kbd> keys.
</p>
<img src="creating_schematic6.png">
<p>
Finally we must connect the input and output port connectors, and to complete the gate schematic
we decide to use W=8u for the pmos transistors. Select both the pmos devices and press the
edit proprty <kbd>'q'</kbd> key; modify from 5u (default) to 8u.
</p>
<img src="creating_schematic7.png">
<p>
Now do a Save as operation, save it for example in <kbd>mylib/nand2.sch</kbd>.<br>
To make the schematic nicer we also add the title component. This component is not netlisted but is
useful, it reports the modification date and the author. Place the <kbd>devices/title.sym</kbd>
component. The NAND gate is completed! (below picture also with grid, normally disabled in pictures
to make image sizes smaller).
</p>
<img src="creating_schematic8.png">
<p>
Normally a cmos gate like the one used in this example is used as a building block (among many others)
for bigger circuits, therefore we need to enclose the schematic view above in a symbol representation.
</p>
<h3>Automatic symbol creation</h3>
<p>
XSCHEM has the ability to automatically generate a symbol view given the schematic view. Just press
the <kbd>'a'</kbd> bindkey in the drawing area of the nand2 gate.
</p>
<img src="creating_schematic9.png">
<p>
After pressing 'OK' a <kbd>mylib/nand2.sym</kbd> file is generated. try opening it
(<kbd>File-&gt;Open</kbd>):
</p>
<img src="creating_schematic10.png">
<p>
As you can see a symbolic view of the gate has been automatically created using the information
in the schematic view (specifically, the input/output pins). Now, this graphic is not really
looking like a nand gate, so we may wish to edit it to make it look better. Delete (by selecting
and pressing the <kbd>Delete</kbd> key) all the green lines, keep the red pins, the pin labels and the
@symname and @name texts, then draw a nand shape like in the following picture.
To allow you to draw small
segments you may need to reduce the snap factor (menu <kbd>View-&gt;Half snap thresholf</kbd>)
remember to reset the snap factor to its default setting when done.
</p>
<img src="creating_schematic11.png">
<p>
This completes the nand2 component. It is now ready to be placed in a schematic. Open a test schematic
(for example <kbd>mylib/test.sch</kbd> (remember to save the nand2.sym you have just created),
press the <kbd>Insert</kbd> key and locate the <kbd>mylib/nand2.sym</kbd> symbol.
Then insert <kbd>devices/lab_pin.sym</kbd> components and place wires to connect some nodes to the
newly instantiated nand2 component:
</p>
<img src="creating_schematic12.png">
<p>
This is now a valid circuit. Let's test it by extracting the SPICE netlist. Enable the showing
of netlist window (<kbd>Options -&gt; Show netlist win</kbd>, or <kbd>'A'</kbd> key).
Now extract the netlist (<kbd>Netlist</kbd> button on the right side of the menu bar, or <kbd>'N'</kbd>
key). the SPICE netlist will be shown.
</p>
<pre class="code">
**.subckt test
x1 OUTPUT_Z INPUT_A INPUT_B nand2
**** begin user architecture code
**** end user architecture code
**.ends
* expanding symbol: mylib/nand2 # of pins=3
.subckt nand2 Z A B
*.ipin A
*.opin Z
*.ipin B
m1 Z A net1 VSS nmos w=5u l=0.18u m=1
m2 Z B VCC VCC pmos w=8u l=0.18u m=1
m3 Z A VCC VCC pmos w=8u l=0.18u m=1
m4 net1 B VSS VSS nmos w=5u l=0.18u m=1
**** begin user architecture code
**** end user architecture code
.ends
.GLOBAL VCC
.GLOBAL VSS
.end
</pre><br>
<p>
This is an example of a hierarchical circuit. The nand2 is a symbol view of another lower level
schematic. We may place multiple times the nand2 symbol to create more complex circuits.
</p>
<img src="creating_schematic13.png">
<p>
By selecting one of the nand2 gates and pressing the <kbd>'e'</kbd> key or menu
<kbd>Edit -&gt; Push schematic</kbd> we can 'descend' into it and navigate through the various
hierarchies. Pressing <kbd>&lt;ctrl&gt;e</kbd> returns back to the upper level.
</p>
<img src="creating_schematic14.png">
<p>
This is the corresponding netlist:
</p>
<pre class="code">
**.subckt test
x1 Q SET_BAR QBAR nand2
x2 QBAR CLEAR_BAR Q nand2
**** begin user architecture code
**** end user architecture code
**.ends
* expanding symbol: mylib/nand2 # of pins=3
.subckt nand2 Z A B
*.ipin A
*.opin Z
*.ipin B
m1 Z A net1 VSS nmos w=5u l=0.18u m=1
m2 Z B VCC VCC pmos w=8u l=0.18u m=1
m3 Z A VCC VCC pmos w=8u l=0.18u m=1
m4 net1 B VSS VSS nmos w=5u l=0.18u m=1
**** begin user architecture code
**** end user architecture code
.ends
.GLOBAL VCC
.GLOBAL VSS
.end
</pre><br>
<p>
The advantage of using hierarchy in circuits is the same as using functions in programming
languages; avoid drawing many repetitive blocks. Also the netlist file will be much smaller.
</p>
<h3>Automatic Component Wiring</h3>
<p>
When a new symbol is placed there is a function to connect its pins to auto-named nets:
select the symbol, then
Press the <kbd>'H'</kbd> key or the <kbd>Symbol-&gt;Attach pins to component instance</kbd> menu entry.
</p>
<img src="auto_wiring1.png">
<p>
The <kbd>use prefix</kbd> will prepend the shown prefix to the wire names to be attached to the component.
The default value for the prefix is the instance name followed by an underscore.<br>
The <kbd>use wire labels</kbd> will use wire labels instead of pin labels. Wire labels have the text name field
offset vertically to allow a wire to pass through without crossing the wire name. in the picture below,
the first component is wired with <kbd>use prefix</kbd> selected and <kbd>use wire labels</kbd> not selected,
the second example with <kbd>use prefix</kbd> not selected and <kbd>use wire labels</kbd> selected. As you
can see in the second example you may draw wires without overstriking the labels.
</p>
<img src="auto_wiring2.png">
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<!DOCTYPE html>
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p{padding: 15px 30px 10px;}
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<h1>CREATING SYMBOLS</h1><br>
<h3> creating a new symbol and schematic by cloning</h3>
<p>
A useful approach to create a new component (both symbol and schematic view) is to 'clone' it
from a similar existing component: after copying a component to a different place in the schematic,
press the edit property bindkey (<kbd>q</kbd> key) and set a new name for the symbol, set also the
<kbd>copy cell</kbd> checkbox:
</p>
<img src="symbol_generation5.png">
<p>
After pressing <kbd>OK</kbd> a copy (both schematic and symbol views) of the previously selected
component will be created. After this clone operation modifications can be made on the newly
created schematic and symbol views without affecting the original component.
</p>
<img src="symbol_generation6.png">
<p> for more info on symbols see the <a href="tutorial_create_symbol.html">Tutorial</a> </p><br>
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<title>DEVELOPER INFO</title>
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<h1>DEVELOPER INFO</h1><br>
<h3>GENERAL INFORMATION</h3>
<p>
XSCHEM uses layers for its graphics, each layer is a logical entity defining graphic attributes
like color and fill style. There are very few graphical primitive objects:
</p>
<ol>
<li>Lines</li>
<li>Rectangles</li>
<li>Open / close Polygons</li>
<li> Arcs / Circles</li>
<li>Text</li>
</ol>
<p>
These primitive objects can be drawn on any layer. XSCHEM number of layers can be defined at compile
time, however there are some predefiend layers (from 0 to 5) that have specific functions:
</p>
<ol start="0">
<li>Background color</li>
<li>Wire color (nets)</li>
<li>Selection color / grid</li>
<li>Text color</li>
<li>Symbol drawing color</li>
<li>Pin color</li>
<li>General purpose</li>
<li>General purpose</li>
<li>General purpose</li>
</ol>
<p style="margin-left:30px;">
....
</p>
<ol start="20">
<li>General purpose</li>
<li>General purpose</li>
</ol>
<p>
Although any layer can be used for drawing it is strongly advisable to avoid the
background color and the selection color to avoid confusion.
Drawing begins by painting the background (layer 0), then drawing the grid (layer 1)
then drawing wires (nets) on layer 2, then all graphical objects (lines, rectangles, polygons)
starting form layer 0 to the last defined layer.
</p>
<h3>SYMBOLS</h3>
<p>
There is a primitive object called symbol. Symbols are just a group of primitive graphic objects
(lines, polygons, rectangles, text) that can be shown as a single atomic entity.
Once created a symbol can be placed in a schematic. The instantiation of a symbol is called 'component'.
</p>
<img src="building_symbol_03.png">
<p>
The above picture shows a resistor symbol, built drawing some lines on layer 4 (green),
some pins on layer 5 (red) and some text.
Symbols once created are stored in libraries (library is just a UNIX directory known to XSCHEM)
and can be placed like just any other primitive object multiple times in a schematic window
with different orientations.
</p>
<img src="developer_info_01.png">
<h3>WIRES</h3>
<p>
Another special primitive object in XSCHEM is 'Wire', Graphically it is drawn as a line on layer 1 (wires).
Wires are drawn only on this layer, they are treated differently by XSCHEM since they carry electrical
information. Electrical connection between components is done by drawing a connecting wire.
</p>
<p class="important">
Since wires are used to build the circuit connectivity it is best to avoid drawing lines on layer 1
to avoid confusion, since they would appear like wires, but ignored completely for electrical connectivity.
</p>
<h3>PROPERTIES </h3>
<p>
All XSCHEM objects (wires, lines, rectangles, polygons, text, symbol instance aka component)
have a property string attached. Any text can be present in a property string, however
in most cases the property string is organized as a set of <kbd>key=value</kbd> pairs separated by white space.
In addition to object properties the schematic or symbol view has global properties attached.
There is one global property defined per netlisting mode (currently SPICE, VHDL, Verilog, tEDAx).
See the <a href="xschem_properties.html">XSCHEM properties</a> section of the manual for more info.
</p>
<h3>COORDINATE SYSTEM</h3>
<p>
XSCHEM coordinates are stored as double precision floating point numbers, axis orientation is the same as Xorg
default coordinate orientation:
</p>
<img src="developer_info_02.png">
<p>
When drawing objecs in XSCHEM coordinates are snapped to a multiple of 10.0 coordinate units,
so all drawn objects are easily aligned.
The snap level can be changed to any value by the user to allow drawing small objects if desired.
Grid points are shown at multiples of 20.0 coordinate units, by default.
</p>
<h2>XSCHEM FILE FORMAT SPECIFICATION</h2>
<p>
XSCHEM schematics and symbols are stored in .sch and .sym files respectively. The two file formats are identical, with the
exception that symbol (.sym) files do not contain wires and component instantiations.
</p>
<p>
every schematic/symbol object has a corresponding record in the file.
A single character at the beginning of a line, separated by white space from subsequent fields marks the type of object:
</p>
<ul>
<li><kbd>v</kbd> : XSCHEM Version string
<li><kbd>S</kbd> : Global property associated to the .sch file for SPICE netlisting</li>
<li><kbd>V</kbd> : Global property associated to the .sch file for VERILOG netlisting</li>
<li><kbd>G</kbd> : Global property associated to the .sch file for VHDL netlisting OR
Global property associated to the .sym file for netlisting</li>
<li><kbd>E</kbd> : Global property associated to the .sch file for tEDAx netlisting</li>
<li><kbd>K</kbd> : Global property associated to the .sch file for netlisting if schematic is instantiated as a component (file format 1.2 and newer) </li>
<li><kbd>L</kbd> : Line </li>
<li><kbd>B</kbd> : Rectangle </li>
<li><kbd>P</kbd> : Open / Closed polygon </li>
<li><kbd>A</kbd> : Arc / Circle </li>
<li><kbd>T</kbd> : Text </li>
<li><kbd>N</kbd> : Wire, used to connect together components (only in .sch files) </li>
<li><kbd>C</kbd> : Component instance in a schematic (only in .sch files) </li>
<li><kbd>[</kbd> : Start of a symbol embedding, the symbol refers to the immediately preceding component instance.
This tag must immediately follow a component instance (<kbd>C</kbd>).
See the example here under. A component symbol is embedded into the schematic file when saving
if the <kbd>embed=true</kbd> attribute is set on one of the component instances.
Only one copy of the embedded symbol is saved into the schematic and all components
referring to this symbol will use the embedded definition.
When a component has an embedded symbol definition immediately following, a <kbd>embed=true</kbd> is
added to the component property string if not already present.
</li><br>
<pre class="code">
C {TECHLIB/PCH} 620 -810 0 0 {name=x5 model=PCHLV w=4 l=0.09 m=1 embed=true}
[
G {type=pmos
format="@name @pinlist @model w=@w l=@l m=@m"
verilog_format="@verilog_gate #(@del ) @name ( @@d , @@s , @@g );"
template=" name=x1 verilog_gate=pmos del=50,50,50 model=PCH w=0.68 l=0.07 m=1 "
generic_type="model=string"
}
V {}
S {}
E {}
L 4 5 20 20 20 {}
L 4 20 20 20 30 {}
L 4 5 -20 20 -20 {}
L 4 20 -30 20 -20 {}
L 4 -20 0 -10 0 {}
L 4 5 -27.5 5 27.5 {11}
L 4 5 -5 10 0 {}
L 4 5 5 10 0 {}
L 4 10 0 20 0 {}
L 18 -2.5 -15 -2.5 15 {}
B 5 17.5 27.5 22.5 32.5 {name=d dir=inout}
B 5 -22.5 -2.5 -17.5 2.5 {name=g dir=in}
B 5 17.5 -32.5 22.5 -27.5 {name=s dir=inout}
B 5 17.5 -2.5 22.5 2.5 {name=b dir=in}
A 4 -6.25 0 3.75 270 360 {}
T {@w/@l*@m} 7.5 -17.5 0 0 0.2 0.2 {}
T {@name} 7.5 6.25 0 0 0.2 0.2 {999}
T {@model} 2.5 -27.5 0 1 0.2 0.2 {layer=8}
T {D} 25 17.5 0 0 0.15 0.15 {layer=13}
T {NF=@nf} -5 -15 0 1 0.15 0.15 {}
]
</pre><br>
<li><kbd>]</kbd> : End of an embedded symbol. </li>
</ul>
<p>
the object tag in column 1 is followed by space separated fields that completely define the corresponding object.
</p>
<h3>VERSION STRING</h3>
<p>
Example: <kbd><br>
v {xschem version=2.8.2_RC3 file_version=1.0}</kbd>
</p>
<p>
Two attributes are defined, the xschem version and the file format version.
Current file format version is 1.0. This string is guaranteed to be the first one in XSCHEM .sch and .sym files.
</p>
<h3>GLOBAL SCHEMATIC/SYMBOL PROPERTIES</h3>
<p>
Example:<kbd><br>
G {type=regulator<br>
format="x@name @pinlist r@symname"<br>
verilog_format="assign @#2 = @#0 ;"<br>
tedax_format="footprint @name @footprint<br>
device @name @symname"<br>
template="name=U1 footprint=TO220"}</kbd>
</p>
<p>
Global properties define a property string bound to the parent schematic/symbol file,
there is one global property record per netlisting mode,
currently SPICE, VHDL, Verilog, tEDAx.<br>
In addition (only in file_format 1.2 and newer) for schematics there is a global attribute ('K')
that defines how to netlist the schematic if placed as a
symbol into another parent schematic (should be set in the same way as the 'G' global attribute for symbols).
Normally only 'G' type property strings are used for symbols and define attributes
telling netlisters what to do with the symbol, while global property
strings in schematic files corresponding to the active netlisting mode of XSCHEM are
copied verbatim to the netlist.<br>
the object tag (S, V, G, E) is followed by the property string enclosed in curly braces
(<kbd>{...}</kbd>). This allows strings to contain any white space and newlines.
Curly braces if present in the string are automatically escaped with the '\' character
by XSCHEM when saving data.<br>
Example of the 4 property string records for a schematic file:<kbd><br>
G {} <br>
V {assign #1500 LDOUT = LDIN +1;<br>
} <br>
E {}<br>
S {}</kbd><br>
in this case only the verilog-related global property has some definition. This is Verilog code that is copied into the output netlist.
</p>
<h3>TEXT OBJECT</h3>
<p>
Example: <kbd>T {3 of 4 NANDS of a 74ls00} 500 -580 0 0 0.4 0.4 {font=Monospace layer=4}</kbd><br>
This line defines a text object, the first field after the type tag is the displayed text,
followed by X and Y coordinates,rotation, mirror,
horizontal and vertical text size and finally a property string defining some text attributes.
<ul>
<li>The displayed text is enclosed in curly braces (<kbd>{...}</kbd>) to allow white space. Literal curly braces
must be escaped if present in the saved string. XSCHEM will automatically add the escapes where needed on save.</li>
<li>X ad Y coordinates are saved and retrieved as double precision floating point numbers.</li>
<li>Rotation and mirror are integers (range [0:3], [0:1] respectively) that define the orientation
of text objects. Using rotation and mirror text can be aligned to any corner of its bounding box, so there are 4 different
alignments for vertical text and 4 different alignments for horizontal text. Below picture shows how text is displayed
with respect to its anchor point.
<img src="developer_info_03.png"></li>
<li> text X and Y sizes are stored as floating point numbers.</li>
<li> Finally a property string is stored with the same syntax as the displayed text field.</li>
</ul>
</p>
<h3>WIRE OBJECT</h3>
<p>
Example: <kbd>N 890 -130 890 -110 {lab=ANALOG_GND}</kbd><br>
The net 'N' tag is followed by the end point coordinates x1,y1 - x2,y2
(stored and read as double precision numbers) and a property string, used in this case to name the net.
</p>
<h3>LINE OBJECT</h3>
<p>
Example: <kbd>L 4 -50 20 50 20 {This is a line on layer 4}</kbd><br>
The line 'L' tag is followed by an integer specifying the graphic layer
followed by the x1,y1 - x2,y2 coordinates of the line and a property string.
</p>
<h3>RECTANGLE OBJECT</h3>
<p>
Example: <kbd>B 5 -62.5 -2.5 -57.5 2.5 {name=IN dir=in pinnumber=1}</kbd><br>
The 'Box' 'B' tag is followed by an integer specifying the graphic layer followed
by the x1,y1 - x2,y2 coordinates of the rectangle
and a final property string. This example defines a symbol pin.
</p>
<h3>OPEN / CLOSED POLYGON OBJECT</h3>
<p>
Example: <kbd>P 3 5 2450 -210 2460 -170 2500 -170 2510 -210 2450 -210 {}</kbd><br>
the Polygon 'P' tag is followed by an integer specifying the layer number,
followed by the number of points (integer),
the x,y coordinates of the polygon points and the property string (empty in this example).
If the last point is coincident to the first point a closed polygon is drawn.
A 'fill=true' arribute may be given to fill a cloded polygon, in this case a polygon line looks like:<br>
<kbd>P 3 5 2450 -210 2460 -170 2500 -170 2510 -210 2450 -210 {fill=true}</kbd><br>
</p>
<h3>ARC OBJECT</h3>
<p>
Example: <kbd>A 3 450 -210 120 45 225 {}</kbd><br>
The Arc 'A' tag is followed by an integer specifying the layer number, followed by the arc x, y center coordinates,
the arc radius, the start angle (measured counterclockwise from the three o'clock direction), the arc sweep angle
(measured counterclockwise from the start angle) and the property string (empty in this example).
Angles are measured in degrees.<br>
<img src="developer_info_07.png">
</p>
<h3>COMPONENT INSTANCE</h3>
<p>
Example: <kbd>C {capa.sym} 890 -160 0 0 {name=C4 m=1 value=10u device="tantalium capacitor"}</kbd><br>
Format: <kbd>C {&lt;symbol reference&gt;} &lt;X coord&gt; &lt;Y coord&gt; &lt;rotation&gt;
&lt;flip&gt; {&lt;attributes&gt;}</kbd><br>
The component instance tag C is followed by a string specifying <kbd>library/symbol</kbd> or only <kbd>symbol</kbd>
(see <a href="tutorial_xschem_libraries.html">This tutorial about symbol references</a>)
followed by the x,y coordinates, rotation (integer range [0:3]),
mirror (integer range [0:1]), and a property string defining various attributes
including the mandatory <kbd>name=...</kbd> attribute.<br>
Orientation and mirror meanings are as follows:<br>
<img src="developer_info_04.png">
</p>
<h3>EXAMPLE OF A COMPLETE SYMBOL FILE (7805.sym)</h3><br>
<pre class="code">
G {type=regulator
format="x@name @pinlist r@symname"
verilog_format="assign @#2 = @#0 ;"
tedax_format="footprint @name @footprint
device @name @symname"
template="name=U1 footprint=TO220"}
V {}
S {}
E {}
L 4 -60 0 -50 0 {}
L 4 50 0 60 0 {}
L 4 -50 -20 50 -20 {}
L 4 50 -20 50 20 {}
L 4 -50 20 50 20 {}
L 4 -50 -20 -50 20 {}
L 4 0 20 0 30 {}
B 5 -62.5 -2.5 -57.5 2.5 {name=IN dir=in pinnumber=1}
B 5 -2.5 27.5 2.5 32.5 {name=GND dir=inout pinnumber=2}
B 5 57.5 -2.5 62.5 2.5 {name=OUT dir=out pinnumber=3}
T {@name} -17.5 -15 0 0 0.2 0.2 {}
T {@symname} -17.5 0 0 0 0.2 0.2 {}
T {@#0:pinnumber} -47.5 -2.5 0 0 0.12 0.12 {}
T {@#1:pinnumber} -2.5 12.5 0 0 0.12 0.12 {}
T {@#2:pinnumber} 47.5 -2.5 0 1 0.12 0.12 {}
</pre>
<img src="developer_info_05.png"><br>
<br>
<h3>EXAMPLE OF A COMPLETE SCHEMATIC FILE (pcb_test1.sch)</h3><br>
<pre class="code">
G {}
V {}
S {}
E {}
B 20 270 -550 860 -290 {}
T {3 of 4 NANDS of a 74ls00} 500 -580 0 0 0.4 0.4 {}
T {EXPERIMENTAL schematic for generating a tEDAx netlist
1) set netlist mode to 'tEDAx' (Options menu -> tEDAx netlist)
2) press 'Netlist' button on the right
3) resulting netlist is in pcb_test1.tdx } 240 -730 0 0 0.5 0.5 {}
N 230 -330 300 -330 {lab=INPUT_B}
N 230 -370 300 -370 {lab=INPUT_A}
N 680 -420 750 -420 {lab=B}
N 680 -460 750 -460 {lab=A}
N 400 -350 440 -350 {lab=B}
N 850 -440 890 -440 {lab=OUTPUT_Y}
N 230 -440 300 -440 {lab=INPUT_F}
N 230 -480 300 -480 {lab=INPUT_E}
N 400 -460 440 -460 {lab=A}
N 550 -190 670 -190 {lab=VCCFILT}
N 590 -130 590 -110 {lab=ANALOG_GND}
N 790 -190 940 -190 {lab=VCC5}
N 890 -130 890 -110 {lab=ANALOG_GND}
N 730 -110 890 -110 {lab=ANALOG_GND}
N 730 -160 730 -110 {lab=ANALOG_GND}
N 590 -110 730 -110 {lab=ANALOG_GND}
N 440 -460 680 -460 {lab=A}
N 500 -420 680 -420 {lab=B}
N 500 -420 500 -350 {lab=B}
N 440 -350 500 -350 {lab=B}
C {title.sym} 160 -30 0 0 {name=l2 author="Stefan"}
C {74ls00.sym} 340 -350 0 0 {name=U1:2 risedel=100 falldel=200}
C {74ls00.sym} 790 -440 0 0 {name=U1:1 risedel=100 falldel=200}
C {lab_pin.sym} 890 -440 0 1 {name=p0 lab=OUTPUT_Y}
C {capa.sym} 590 -160 0 0 {name=C0 m=1 value=100u device="electrolitic capacitor"}
C {74ls00.sym} 340 -460 0 0 {name=U1:4 risedel=100 falldel=200 power=VCC5
url="http://www.engrcs.com/components/74LS00.pdf".sym}
C {LM7805.pdf"}
C {lab_pin.sym} 490 -190 0 0 {name=p20 lab=VCC12}
C {lab_pin.sym} 940 -190 0 1 {name=p22 lab=VCC5}
C {lab_pin.sym} 590 -110 0 0 {name=p23 lab=ANALOG_GND}
C {capa.sym} 890 -160 0 0 {name=C4 m=1 value=10u device="tantalium capacitor"}
C {res.sym} 520 -190 1 0 {name=R0 m=1 value=4.7 device="carbon resistor"}
C {lab_wire.sym} 620 -460 0 0 {name=l3 lab=A}
C {lab_wire.sym} 620 -420 0 0 {name=l0 lab=B}
C {lab_wire.sym} 650 -190 0 0 {name=l1 lab=VCCFILT}
C {connector.sym} 230 -370 0 0 {name=CONN1 lab=INPUT_A verilog_type=reg}
C {connector.sym} 230 -330 0 0 {name=CONN2 lab=INPUT_B verilog_type=reg}
C {connector.sym} 240 -190 0 0 { name=CONN3 lab=OUTPUT_Y }
C {connector.sym} 230 -480 0 0 {name=CONN6 lab=INPUT_E verilog_type=reg}
C {connector.sym} 230 -440 0 0 {name=CONN8 lab=INPUT_F verilog_type=reg}
C {connector.sym} 240 -160 0 0 { name=CONN9 lab=VCC12 }
C {connector.sym} 240 -130 0 0 { name=CONN14 lab=ANALOG_GND verilog_type=reg}
C {connector.sym} 240 -100 0 0 { name=CONN15 lab=GND verilog_type=reg}
C {code.sym} 1030 -280 0 0 {name=TESTBENCH_CODE only_toplevel=false value="initial begin
$dumpfile(\\"dumpfile.vcd\\");
$dumpvars;
INPUT_E=0;
INPUT_F=0;
INPUT_A=0;
INPUT_B=0;
ANALOG_GND=0;
#10000;
INPUT_A=1;
INPUT_B=1;
#10000;
INPUT_E=1;
INPUT_F=1;
#10000;
INPUT_F=0;
#10000;
INPUT_B=0;
#10000;
$finish;
end
assign VCC12=1;
"}
C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns" }
</pre>
<img src="developer_info_06.png"><br>
<br>
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<!DOCTYPE html>
<html>
<head>
<title>XSCHEM TUTORIAL</title>
<link rel="stylesheet" type="text/css" href="xschem_man.css" />
<style type="text/css">
/* Local styling goes here */
p{padding: 15px 30px 10px;}
</style>
</head>
<body>
<!-- start of slide -->
<div class="content">
<!-- navigation buttons -->
<a href="xschem_man.html" class="home">UP</a>
<!-- slide title -->
<h1> FAQ </h1>
<h3> I want new instances to get assigned a new unique name automatically.</h3>
<p class="faq">
Add this to your xschemrc file:
</p>
<pre class="code">set disable_unique_names 0</pre>
<p class="faq">
By default XSCHEM allows instance name (Refdes) duplicates in the schematic.
This must be resolved by the user normally, before exporting any netlist.
The <kbd>Hilight - Highlight duplicate instance names</kbd> (<kbd>k</kbd> key) menu entry
can be used to mark the components that need to be renamed.
The <kbd>Highlight - Rename duplicate instance names</kbd> menu entry can be used to automatically
rename the last added components so that they have an unique name.
Using the above mentioned xschemrc option will automatically rename any added refdes
that clashes with existing names.
</p>
<h3> Why do i have to press 'm' to move a component instead of just click and drag? </h3>
<p class="faq">
XSCHEM is intended to handle very big schematics, mouse drags are used to select a rectangular portion
of the circuit to move / stretch, if a mouse click + drag moves components it would be very easy to move
things instead of selecting things. This happens with geda-gschem for example: <br>
<img src="faq00.png"><br>
Here i want to select the R7 and R8 resistors, so i place the mouse close to the upper-left R7 boundary and
start dragging, but since clicking also selects nearby objects the wire gets selected and moving the mouse will move the wire.<br>
<img src="faq01.png"><br>
This behavior is considered not acceptable so clicking and dragging will never modify the circuit.
Pressing 'm' (for move) or 'c' (for copy) makes the behavior more predictable and safer. A new user just needs to get used to it.
</p>
<h3> </h3>
<p class="faq">
</p>
<h3> </h3>
<p class="faq">
</p>
<h3> </h3>
<p class="faq">
</p>
<h3> </h3>
<p class="faq">
</p>
<h3> </h3>
<p class="faq">
</p>
<h3> </h3>
<p class="faq">
</p>
<!-- end of slide -->
<div class="filler"></div>
</div>
<!-- frame footer -->
<iframe seamless src="xschem_footer.html" class="footer_iframe" >
</body>
</html>

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/* XPM */
static char *icon[] = {
/* width height num_colors chars_per_pixel */
" 60 41 5 1",
/* colors */
". c #000000",
"# c #00a8e8",
"a c #787c78",
"b c #88dc00",
"c c #b00000",
/* pixels */
"............................................................",
"............................................................",
"............................................................",
"............................................................",
".......a...........a...........a...........a...........a....",
"............................................................",
"...................bbbb.....................bbbb............",
"....................b.........................b.............",
"....................c........................cb.............",
"..................b.b......................b..b.............",
"..................bbb......................bbbb.............",
".................bb.......................bb................",
"................bbb......................bbb................",
"..............cbbbb....................cbbbb................",
"...............#bbb.....................#bbb................",
"...............#.bb.....................#.bb................",
".......a.......#..bbb..........a........#..bbbb........a....",
"...............#..b.c...................#..b.cb.............",
"...............#....#...................#.....#.............",
"...............#....#...................#.....#.............",
"......cccc######....#####################.....##############",
"......ccc......#....#...................#.....#.............",
"...............#....#...................#.....#.............",
"...............#....c...................#....cb.............",
"...............#..b.b...................#..b..b.............",
"...............#..bbb...................#..bbbb.............",
"...............#.bb.....................#.bb................",
"...............#.bb.....................#.bb................",
".......a......cbbbba...........a.......cbbbb...........a....",
".................bb.......................bb................",
".................bb.......................bb................",
"..................bbb......................bbbb.............",
"..................b.c......................b.cb.............",
"....................b.........................b.............",
"....................bb.......................bb.............",
"....................b.........................b.............",
"............................................................",
"............................................................",
"............................................................",
"............................................................",
".......a...........a...........a...........a...........a...."
};

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<!DOCTYPE html>
<html>
<head>
<title>XSCHEM TUTORIAL</title>
<link rel="stylesheet" type="text/css" href="xschem_man.css" />
<style type="text/css">
/* Local styling goes here */
p{padding: 15px 30px 10px;}
</style>
</head>
<body>
<!-- start of slide -->
<div class="content">
<!-- navigation buttons -->
<a href="what_is_xschem.html" class="prev">PREV</a>
<a href="xschem_man.html" class="home">UP</a>
<a href="run_xschem.html" class="next">NEXT</a>
<!-- slide title -->
<h1> INSTALL XSCHEM </h1><br>
<p>
in order to install the program run the following command:
</p>
<pre class="code">
user:~$ cd xschem-&lt;version&gt;; ./configure
</pre>
<p>
This will make all the necessary checks for required libraries and system tools.
</p>
<p>
for Debian and Ubuntu systems these are the packages you should check to be installed.
Tck/Tk versions may vary on different systems, 8.4, 8.5, 8.6 versions are all good.
</p>
<pre class="code">
tcl8.6 libx11-dev
tk8.6 libxpm-dev
tcl8.6-dev bison
tk8.6-dev flex
gawk or mawk libcairo2-dev
</pre>
<p>If configure ends with no errors we are ready to compile:
</p>
<pre class="code">
user:~$ make
</pre>
<p>If we want to install xschem and its required files (execute as root if you plan to do a system-wide
installation, for example in /usr/local):
</p>
<pre class="code">
user:~$ make install
</pre>
<p>
This will install all the runtime needed files into the locations previously configured
(can be found in Makefile.conf). To change the default installation prefix
(/usr/local), please replace the configure step shown above with:
</p>
<pre class="code">
./configure --prefix=new/prefix/path
</pre>
<p>
DESTDIR is supported.
</p>
<p class="important">
For testing purposes <kbd>xschem</kbd> can be run and invoked from the build directory
<kbd>xschem-&lt;version&gt;/src/</kbd> without installation.
</p><br>
<pre class="code">
user:~$ cd xschem-2.7.0/src && ./xschem
</pre>
<p>
When xschem is running, type <kbd>puts $XSCHEM_LIBRARY_PATH</kbd> in the xschem tcl prompt to
know the library search path.<br>
Type <kbd>puts $XSCHEM_SHAREDIR</kbd> to see the installation path.
</p>
<p>
Sample user design libraries are provided and installed systemwide under
<kbd>${XSCHEM_SHAREDIR/xschem_library/</kbd>.
The XSCHEM_START_WINDOW specifies a schematic to preload at startup, to avoid absolute paths use a path that
is relative to one of the <kbd>XSCHEM_LIBRARY_PATH</kbd> directories. XSCHEM will figure out the actual location.
You may comment the definition if you don't want any schematic on startup.
<br><br>
If you need to override system settings, create a
<kbd>~/.xschem/xschemrc</kbd>. The easiest way is to copy the system
installed version from ${prefix}/share/xschem/xschemrc and then
make the necessary changes
</p>
<pre class="code">
user:$ mkdir ~/.xschem
user:$ cp &lt;install root&gt;/share/xschem/xschemrc ~/.xschem/xschemrc
</pre><br>
<br><br>
<h2> -Technical information - Detailed XSCHEM startup sequence </h2>
<p class="important"> Information here under is not meant to be executed by the user </p><br>
<ol>
<li>If <kbd>--rcfile=&lt;rcfile&gt;</kbd> is given then source the specified rcfile. Do not load any other rcfile.</li>
<li>If <kbd>../src/xchem.tcl</kbd> with respect to current dir is existing and
<kbd>../xschem_library</kbd> is also existing then we are starting
from a build directory, set <kbd>XSCHEM_SHAREDIR</kbd> to <kbd>&lt;current dir&gt;</kbd> and
also set <br><kbd>XSCHEM_LIBRARY_PATH</kbd> to <kbd>.:/../xschem_library/devices</kbd>.</li>
<li>Else use compile-time (generated from configure script) provided <kbd>XSCHEM_SHAREDIR</kbd>.
<li>Source system-wide xschemrc if existing: <kbd>XSCHEM_SHAREDIR/xschemrc</kbd></li>
<li>If in current dir there is a <kbd>xschemrc</kbd> file source it.</li>
<li>Else if there is a <kbd>USER_CONF_DIR/xschemrc</kbd> file source it.
<kbd>XSCHEM_SHAREDIR</kbd> and <kbd>USER_CONF_DIR</kbd> are preprocessor macros
passed at compile time by the configure script.
The first one will be overridden only if executing from a build directory, see item 2.</li>
<li>If <kbd>XSCHEM_SHAREDIR</kbd> not defined --&gt; error and quit.</li>
<li>Start loading user provided schematic file or start with empty window (or filename
specified in <kbd>XSCHEM_START_WINDOW</kbd> tcl variable).</li>
</ol>
<br><br>
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<!DOCTYPE html>
<html>
<head>
<title>NET PROBES</title>
<link rel="stylesheet" type="text/css" href="xschem_man.css" />
<style type="text/css">
/* Local styling goes here */
p{padding: 15px 30px 10px;}
</style>
</head>
<body>
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<div class="content">
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<!-- slide title -->
<h1>NET PROBES</h1><br>
<p>
XSCHEM has the ability to hilight a net and propagate the highlight color to all nets or
instance pins attached to the net. It has the ability to follow this net through the hierarchy. This is very
useful in large designs as it makes it easy to see where a net is driven and were the net goes (fan-out).
Highlighting a net is straightforward, click a net and press the <kbd>'k'</kbd> key. If more nets are selected
all nets will be colored with different colors.
<kbd>&lt;Shift&gt;K</kbd> clears all highlight nets, <kbd>&lt;Ctrl&gt;k</kbd> clears selected nets.
</p>
<p>Select some nets...</p>
<img src="probes1.png">
<p>...press the <kbd>'k'</kbd> key...</p>
<img src="probes2.png">
<p>...all nets are highlighted, select the white net...</p>
<img src="probes3.png">
<p>..press the <kbd>&lt;Ctrl&gt;k</kbd> key and white net is un-highlighted...</p>
<img src="probes4.png">
<p>
if you descend into component instance <kbd>x1</kbd> (mos_power_ampli) (<kbd>'e'</kbd> key) you will see the highlight nets
propagated into the child component.
</p>
<img src="probes5.png">
<p>
A very useful function is the 'View only probes' mode, (<kbd>'5'</kbd> key) that hides
everything but the highlight probes. This is useful in very big VLSI designs to quickly
locate start and end point of nets.
Pressing again the <kbd>'5'</kbd> key restores the normal view.
</p>
<img src="probes6.png">
<br>
<img src="probes7.png">
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<!DOCTYPE html>
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<head>
<title>NETLISTING</title>
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<style type="text/css">
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p{padding: 15px 30px 10px;}
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<h1>NETLISTING</h1><br>
<p>
XSCHEM has 3 predefined netlisting modes, <kbd>Spice</kbd>, <kbd>Verilog</kbd> and
<kbd>VHDL</kbd>. Netlisting mode can be set in the <kbd>Options</kbd> menu
(<kbd>Vhdl</kbd>, <kbd>Verilog</kbd> <kbd>Spice</kbd> radio buttons)
or with the <kbd>&lt;Shift&gt;V</kbd> key. Once a netlist mode is set, hitting the
<kbd>Netlist</kbd> button on the top-right of the menu bar or the <kbd>&lt;Shift&gt;N</kbd>
key will produce the netlist file in the defined simulation directory.
The simulation directory is one important path that is specified in the <kbd>xschemrc</kbd>
file, if no one is defined XSCHEM will prompt for a directory.
The path where netlists are produced can be changed with the
<kbd>Simulation-&gt;Set netlist dir</kbd> menu entry.
The netlist filename is <kbd>cellname.ext</kbd> where <kbd>cellname</kbd> is the name of the
top-level schematic from which the netlist has been generated, and <kbd>ext</kbd> is the
file extension:</p>
<ul>
<li><kbd>spice</kbd> for spice netlist.</li>
<li><kbd>vhdl</kbd> for vhdl netlist.</li>
<li><kbd>v</kbd> for verilog netlist.</li>
</ul>
<h3> EXAMPLE</h3>
<p>
Consider the following top level schematic, part of the XSCHEM distribution
(<kbd>examples/poweramp.sch</kbd>).</p>
<img src="netlisting1.png">
<p>
This schematic is made of some <kbd>leaf</kbd> components and some
<kbd>subcircuit</kbd> components:
</p>
<ul>
<li><kbd>leaf</kbd>: these componens are 'known' to the simulator,
netlist of these blocks is done by specifying a 'format' attribute in the symbol
property string. Examples of leaf components in the schematic above are voltage sources,
resistors, capacitors, dependent sources. The following are examples of leaf component
instantiations in a SPICE netlist:<br><br>
<pre class="code">
c3 VSS VNN 100u m=1
r11 VPP net1 0.3 m=1
r9 VNN net2 0.3 m=1
r19 OUTM FBN '100k' m=1
</pre><br>
The format of resistor (and capacitor) SPICE netlist is defined in the
format attribute of the symbol global property: <br><br>
<pre class="code">
format="@name @pinlist @value m=@m"</pre>
</li><br>
<li><kbd>subcircuit</kbd>: these components are not base blocks known to the simulator, but
are representation of a more complex block. These components have in addition to the symbol
a schematic representation. In the picture example the <kbd>mos_power_ampli</kbd> is a
subcircuit block. These type of components also have a 'format' property that defines
a subcircuit call. A subcircuit call specifies the connections of nets to the symbol pins
and the symbol name. The following two subcircuit calls are present in the SPICE
netlist:<br><br>
<pre class="code">
x1 OUTM VSSX FBN VPP VNN VSS mos_power_ampli
x0 OUTP INX FB VPP VNN VSS mos_power_ampli</pre>
<br>
The format of subcircuit type components is also defined in the symbol <kbd>format</kbd>
attribute: <br><br>
<pre class="code">
format="@name @pinlist @symname"</pre>
</li>
</ul>
<p>
For subcircuits, after completing the netlist of the top level the XSCHEM' netlister
will recursively generate all the netlists of subcircuit components until leaf
schematics are reached that do not instantiate further subcircuits.
</p>
<pre class="code">
...
... (end of top level netlist)
...
* expanding symbol: examples/mos_power_ampli # of pins=6
.subckt mos_power_ampli OUT PLUS MINUS VPP VNN VSS
*.ipin PLUS
*.ipin MINUS
*.ipin VPP
...
... </pre>
<br>
<h3> Other netlist formats</h3>
<p>
All the concepts explained for SPICE netlist apply for Verilog and VHDL formats.
Its up to the designer to ensure that the objects in the schematic are 'known' to the
target simulator. For example a resistor is normally
not used in VHDL or Verilog designs, so unless an appropriate 'format'
attribute is defined (for example a <kbd>rtran</kbd> device may be good for a verilog
resistor with some limitations).
The format attribute for Verilog is called <kbd>verilog_format</kbd> and
the attribute for VHDL is <kbd>vhdl_format</kbd><br>
The following example shows two attributes in a NMOS symbol that define the format
for SPICE and for Verilog and some valid default (<kbd>template</kbd>) values:
</p>
<pre class="code">
type=nmos
format="@name @pinlist @model w=@w l=@l m=@m"
verilog_format="@verilog_gate #(@del ) @name ( @@d , @@s , @@g );"
template="name=x1 verilog_gate=nmos del=50,50,50 model=NCH w=0.68 l=0.07 m=1"
generic_type="model=string" </pre>
<br>
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