refactoring of netlister code
This commit is contained in:
Stefan Frederik
parent
945a26c8f6
commit
6be0fc392b
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@ -15,28 +15,27 @@
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#### XSCHEM SYSTEM-WIDE DESIGN LIBRARY PATHS: XSCHEM_LIBRARY_PATH
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###########################################################################
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#### If unset xschem starts with XSCHEM_LIBRARY_PATH set to the default, typically:
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# /home/schippes/.xschem/xschem_library
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# /home/schippes/share/xschem/xschem_library/devices
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# /home/schippes/share/doc/xschem/examples
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# /home/schippes/share/doc/xschem/ngspice
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# /home/schippes/share/doc/xschem/logic
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# /home/schippes/share/doc/xschem/xschem_simulator
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# /home/schippes/share/doc/xschem/binto7seg
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# /home/schippes/share/doc/xschem/pcb
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# /home/schippes/share/doc/xschem/rom8k
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#### /home/schippes/.xschem/xschem_library
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#### /home/schippes/share/xschem/xschem_library/devices
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#### /home/schippes/share/doc/xschem/examples
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#### /home/schippes/share/doc/xschem/ngspice
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#### /home/schippes/share/doc/xschem/logic
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#### /home/schippes/share/doc/xschem/xschem_simulator
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#### /home/schippes/share/doc/xschem/binto7seg
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#### /home/schippes/share/doc/xschem/pcb
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#### /home/schippes/share/doc/xschem/rom8k
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#### For testing in build src directory
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#### if unset following paths are set and maintained if existing:
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#
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# ~/.xschem/xschem_library
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# ../xschem_library/devices
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# ../xschem_library/examples
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# ../xschem_library/ngspice
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# ../xschem_library/logic
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# ../xschem_library/xschem_simulator
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# ../xschem_library/binto7seg
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# ../xschem_library/pcb
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# ../xschem_library/rom8k
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#### ~/.xschem/xschem_library
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#### ../xschem_library/devices
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#### ../xschem_library/examples
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#### ../xschem_library/ngspice
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#### ../xschem_library/logic
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#### ../xschem_library/xschem_simulator
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#### ../xschem_library/binto7seg
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#### ../xschem_library/pcb
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#### ../xschem_library/rom8k
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#### For testing after installation: uncomment following lines
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# set xschem_doc_dir [file dirname ${XSCHEM_SHAREDIR}]/doc/xschem
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@ -185,6 +184,11 @@
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#### editing a new component if clicking on a new component.
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#### default: enabled (1)
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# set autofocus_mainwindow 0
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#### set component browser always above drawing canvas.
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#### default: enabled (1)
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# set component_browser_on_top 0
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###########################################################################
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#### EXPORT FORMAT TRANSLATORS, PNG AND PDF
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###########################################################################
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@ -342,40 +346,40 @@ set editor {notepad.exe}
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###########################################################################
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#### TABBED WINDOWS
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###########################################################################
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# default: not enabled. Interface can be changed runtime if only one window
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# or tab is open.
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#### default: not enabled. Interface can be changed runtime if only one window
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#### or tab is open.
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# set tabbed_interface 1
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###########################################################################
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#### CASE INSENSITIVE SYMBOL LOOKUP
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###########################################################################
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## this option might be useful on filesystems that are case insensitive and
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## on designs ported from windows where case of file names does not matter.
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## if this option is set symbol lookup will be case insensitive,
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## so a symbol reference 'AMPLI.SYM' will match with 'ampli.sym' or
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## Amply.sym on disk. File system must be case insensitive for this to work,
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## like FAT32 or NTFS.
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## Do not set this option if you don't know what you are doing.
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## Default: not enabled (0)
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#### this option might be useful on filesystems that are case insensitive and
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#### on designs ported from windows where case of file names does not matter.
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#### if this option is set symbol lookup will be case insensitive,
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#### so a symbol reference 'AMPLI.SYM' will match with 'ampli.sym' or
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#### Amply.sym on disk. File system must be case insensitive for this to work,
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#### like FAT32 or NTFS.
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#### Do not set this option if you don't know what you are doing.
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#### Default: not enabled (0)
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# set case_insensitive 1
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###########################################################################
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#### SHOW HIDDEN TEXTS
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###########################################################################
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## This option shows text objects even if they have attribute 'hide=true' set
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## default: 0 (not set)
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#### This option shows text objects even if they have attribute 'hide=true' set
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#### default: 0 (not set)
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# set show_hidden_texts 1
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###########################################################################
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#### HIDE GRAPHS IF NO SPICE DATA LOADED
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###########################################################################
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## if enabled graphs will be hidden if no data is loaded.
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## default: not enabled (0)
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#### if enabled graphs will be hidden if no data is loaded.
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#### default: not enabled (0)
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# set hide_empty_graphs 0
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###########################################################################
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#### LIVE BACKANNOTATION OF DATA AT CURSOR 2 (B) POSITION
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###########################################################################
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## if enabled will backannotate values in schematic at cursor 'b' position
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## in graph. Default: not enabled (0)
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#### if enabled will backannotate values in schematic at cursor 'b' position
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#### in graph. Default: not enabled (0)
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# set live_cursor2_backannotate 1
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@ -1131,9 +1131,12 @@ int callback(const char *winpath, int event, int mx, int my, KeySym key,
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xctx->mousey=Y_TO_XSCHEM(my);
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xctx->mousex_snap=my_round(xctx->mousex / c_snap) * c_snap;
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xctx->mousey_snap=my_round(xctx->mousey / c_snap) * c_snap;
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my_snprintf(str, S(str), "mouse = %.16g %.16g - selected: %d path: %s",
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xctx->mousex_snap, xctx->mousey_snap, xctx->lastsel, xctx->sch_path[xctx->currsch] );
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statusmsg(str,1);
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if(abs(mx-xctx->mx_save) > 8 || abs(my-xctx->my_save) > 8 ) {
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my_snprintf(str, S(str), "mouse = %.16g %.16g - selected: %d path: %s",
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xctx->mousex_snap, xctx->mousey_snap, xctx->lastsel, xctx->sch_path[xctx->currsch] );
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statusmsg(str,1);
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}
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switch(event)
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{
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@ -1201,12 +1204,14 @@ int callback(const char *winpath, int event, int mx, int my, KeySym key,
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#endif
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if(xctx->semaphore >= 2) break;
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if(xctx->ui_state) {
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my_snprintf(str, S(str), "mouse = %.16g %.16g - selected: %d w=%.16g h=%.16g",
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xctx->mousex_snap, xctx->mousey_snap,
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xctx->lastsel ,
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xctx->mousex_snap-xctx->mx_double_save, xctx->mousey_snap-xctx->my_double_save
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);
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statusmsg(str,1);
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if(abs(mx-xctx->mx_save) > 8 || abs(my-xctx->my_save) > 8 ) {
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my_snprintf(str, S(str), "mouse = %.16g %.16g - selected: %d w=%.16g h=%.16g",
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xctx->mousex_snap, xctx->mousey_snap,
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xctx->lastsel ,
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xctx->mousex_snap-xctx->mx_double_save, xctx->mousey_snap-xctx->my_double_save
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);
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statusmsg(str,1);
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}
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}
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if(xctx->ui_state & STARTZOOM) zoom_rectangle(RUBBER);
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if(xctx->ui_state & STARTSELECT && !(xctx->ui_state & (PLACE_SYMBOL | STARTPAN | PLACE_TEXT)) ) {
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13
src/check.c
13
src/check.c
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@ -381,10 +381,8 @@ void trim_wires(void)
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void break_wires_at_pins(void)
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{
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int k, i, j, r, rects, sqx, sqy;
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short rot, flip;
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Wireentry *wptr;
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xRect *rct;
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double x0, y0, rx1, ry1;
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double x0, y0;
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int changed=0;
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hash_wires();
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@ -398,14 +396,7 @@ void break_wires_at_pins(void)
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{
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for(r=0;r<rects;r++)
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{
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rct=(xctx->inst[k].ptr+ xctx->sym)->rect[PINLAYER];
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x0=(rct[r].x1+rct[r].x2)/2;
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y0=(rct[r].y1+rct[r].y2)/2;
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rot=xctx->inst[k].rot;
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flip=xctx->inst[k].flip;
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ROTATION(rot, flip, 0.0,0.0,x0,y0,rx1,ry1);
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x0=xctx->inst[k].x0+rx1;
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y0=xctx->inst[k].y0+ry1;
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get_inst_pin_coord(k, r, &x0, &y0);
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get_square(x0, y0, &sqx, &sqy);
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for(wptr=xctx->wire_spatial_table[sqx][sqy]; wptr; wptr=wptr->next) {
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i = wptr->n;
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@ -51,8 +51,14 @@ vhdl_netlist.c \
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xinit.c \
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| sort -n \
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| awk '{
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if(n>0 && $1 <= prev) print ">>>>>>>>>>> ERROR >>>>>>>>>"
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else if(n++>0 && $1 != prev+1) print ">>>>>>>>>>>>>>>>>>>>>>>>>>>"
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if(n>0 && $1 <= prev) print ">>>>>>>>>>> ERROR >>>>>>>>> " $0
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else if(n++>0 && $1 != prev+1) {
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if($1-1 > prev+1)
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print ">>>>>>>>>>> FREE >>>>>>>>> " prev+1 ":" $1-1
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else
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print ">>>>>>>>>>> FREE >>>>>>>>> " $1-1
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print
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} else print
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prev = $1
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print
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}'
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1105
src/netlist.c
1105
src/netlist.c
File diff suppressed because it is too large
Load Diff
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@ -43,9 +43,11 @@ static Node_hashentry *node_hash_lookup(const char *token, const char *dir,int w
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dbg(3, "node_hash_lookup(): called with: %s dir=%s what=%d port=%d\n",
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token, dir, what, port);
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d.in=d.out=d.inout=0;
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if(!strcmp(dir,"in") ) d.in=1;
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else if(!strcmp(dir,"out") ) d.out=1;
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else if(!strcmp(dir,"inout") ) d.inout=1;
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if(dir) {
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if(!strcmp(dir,"in") ) d.in=1;
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else if(!strcmp(dir,"out") ) d.out=1;
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else if(!strcmp(dir,"inout") ) d.inout=1;
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}
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d.port=port;
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hashcode=str_hash(token);
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index=hashcode % HASHSIZE;
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23
src/select.c
23
src/select.c
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@ -45,18 +45,11 @@ static void check_connected_wire(int stop_at_junction, int n)
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k = instptr->n;
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type = (xctx->inst[k].ptr+ xctx->sym)->type;
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if( type && (IS_LABEL_SH_OR_PIN(type) || !strcmp(type, "probe") || !strcmp(type, "ngprobe"))) {
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double rx1, ry1, x0, y0;
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int rot, flip;
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double x0, y0;
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xRect *rct;
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rct=(xctx->inst[k].ptr+ xctx->sym)->rect[PINLAYER];
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if(rct) {
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x0=(rct[0].x1+rct[0].x2)/2;
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y0=(rct[0].y1+rct[0].y2)/2;
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rot=xctx->inst[k].rot;
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flip=xctx->inst[k].flip;
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ROTATION(rot, flip, 0.0,0.0,x0,y0,rx1,ry1);
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x0=xctx->inst[k].x0+rx1;
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y0=xctx->inst[k].y0+ry1;
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get_inst_pin_coord(k, 0, &x0, &y0);
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touches = touch(wire[n].x1, wire[n].y1, wire[n].x2, wire[n].y2, x0, y0);
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if(touches) {
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xctx->need_reb_sel_arr=1;
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@ -106,19 +99,13 @@ void select_connected_wires(int stop_at_junction)
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case ELEMENT:
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type = (xctx->inst[i].ptr+ xctx->sym)->type;
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if( type && (IS_LABEL_SH_OR_PIN(type) || !strcmp(type, "probe") || !strcmp(type, "ngprobe"))) {
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double rx1, ry1, x0, y0;
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int rot, flip, sqx, sqy;
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double x0, y0;
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int sqx, sqy;
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xRect *rct;
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Wireentry *wptr;
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rct = (xctx->inst[i].ptr+ xctx->sym)->rect[PINLAYER];
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if(rct) {
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x0 = (rct[0].x1 + rct[0].x2) / 2;
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y0 = (rct[0].y1 + rct[0].y2) / 2;
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rot = xctx->inst[i].rot;
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flip = xctx->inst[i].flip;
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ROTATION(rot, flip, 0.0,0.0,x0,y0,rx1,ry1);
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x0 = xctx->inst[i].x0+rx1;
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y0 = xctx->inst[i].y0+ry1;
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get_inst_pin_coord(i, 0, &x0, &y0);
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get_square(x0, y0, &sqx, &sqy);
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wptr = xctx->wire_spatial_table[sqx][sqy];
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while (wptr) {
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@ -1122,6 +1122,7 @@ extern int text_bbox(const char * str,double xscale, double yscale,
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extern int get_color(int value);
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extern void incr_hilight_color(void);
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extern void hash_inst(int what, int n);
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extern void get_inst_pin_coord(int i, int j, double *x, double *y);
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extern void del_inst_table(void);
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extern void hash_wires(void);
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extern void hash_wire(int what, int n, int incremental);
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@ -21,7 +21,7 @@ end}
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S {}
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E {}
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C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"}
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C {ipin.sym} 210 -220 0 0 {name=p1 lab=A}
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C {ipin.sym} 210 -220 0 0 {name=p1 lab=A[3:0]}
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C {ipin.sym} 210 -190 0 0 {name=p3 lab=B}
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C {opin.sym} 520 -240 0 0 {name=p4 lab=Z}
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C {ipin.sym} 210 -260 0 0 {name=p5 lab=RST}
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@ -1,7 +1,8 @@
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v {xschem version=3.0.0 file_version=1.2 }
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v {xschem version=3.1.0 file_version=1.2
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}
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G {}
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K {type=subcircuit
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format="@name @@A @@B @@CK @@RST @@Z @symname"
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format="@name @@A[3:0] @@B @@CK @@RST @@Z @symname"
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template="name=x1"
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}
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V {}
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@ -38,10 +39,10 @@ L 4 135 10 140 5 {}
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L 4 135 10 140 15 {}
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L 4 135 45 140 50 {}
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L 4 135 55 140 50 {}
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B 5 -152.5 -12.5 -147.5 -7.5 {name=A dir=in }
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B 5 -152.5 -12.5 -147.5 -7.5 {name=A[3:0] dir=in }
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B 5 -152.5 7.5 -147.5 12.5 {name=B dir=in }
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B 5 147.5 47.5 152.5 52.5 {name=Z dir=out }
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B 5 147.5 -12.5 152.5 -7.5 {name=A dir=in }
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B 5 147.5 -12.5 152.5 -7.5 {name=A[3:0] dir=in }
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B 5 -152.5 -32.5 -147.5 -27.5 {name=CK dir=in }
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B 5 147.5 -32.5 152.5 -27.5 {name=CK dir=in }
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B 5 -152.5 -52.5 -147.5 -47.5 {name=RST dir=in }
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@ -49,8 +50,8 @@ B 5 147.5 -52.5 152.5 -47.5 {name=RST dir=in }
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B 5 147.5 7.5 152.5 12.5 {name=B dir=in }
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T {@symname} -58.5 -6 0 0 0.3 0.3 {}
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T {@name} 105 -72 0 0 0.2 0.2 {}
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T {A} 125 -14 0 1 0.2 0.2 {}
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T {A} -125 -14 0 0 0.2 0.2 {}
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T {A[3:0]} 125 -14 0 1 0.2 0.2 {}
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T {A[3:0]} -125 -14 0 0 0.2 0.2 {}
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T {Z} 125 46 0 1 0.2 0.2 {}
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T {B} -125 6 0 0 0.2 0.2 {}
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T {CK} -125 -34 0 0 0.2 0.2 {}
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@ -58,3 +59,12 @@ T {CK} 125 -34 0 1 0.2 0.2 {}
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T {RST} -125 -54 0 0 0.2 0.2 {}
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T {RST} 125 -54 0 1 0.2 0.2 {}
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T {B} 125 6 0 1 0.2 0.2 {}
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T {@#6:net_name} -127.5 -61.25 0 0 0.15 0.15 {layer=15}
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T {@#4:net_name} -127.5 -41.25 0 0 0.15 0.15 {layer=15}
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T {@#0:net_name} -127.5 -21.25 0 0 0.15 0.15 {layer=15}
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T {@#1:net_name} -127.5 -1.25 0 0 0.15 0.15 {layer=15}
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T {@#7:net_name} 127.5 -61.25 0 1 0.15 0.15 {layer=15}
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T {@#5:net_name} 127.5 -41.25 0 1 0.15 0.15 {layer=15}
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T {@#3:net_name} 127.5 -21.25 0 1 0.15 0.15 {layer=15}
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T {@#8:net_name} 127.5 -1.25 0 1 0.15 0.15 {layer=15}
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T {@#2:net_name} 127.5 38.75 0 1 0.15 0.15 {layer=15}
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@ -24,21 +24,13 @@ vvss vss 0 dc 0
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.tran 1n 200n}
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E {}
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T {OK!} 500 -1020 0 0 1 1 {layer=4}
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T {OK!} 500 -1250 0 0 1 1 {layer=4}
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T {OK!} 500 -1480 0 0 1 1 {layer=4}
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T {Spice netlist allows duplicated pins on symbols} 50 -1570 0 0 1 1 {}
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T {OK!} 500 -790 0 0 1 1 {layer=4}
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T {OK!} 500 -580 0 0 1 1 {layer=4}
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T {OK!} 1320 -1160 0 0 1 1 {layer=4}
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T {OK!} 1320 -1430 0 0 1 1 {layer=4}
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T {OK!} 500 -350 0 0 1 1 {layer=4}
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N 480 -930 630 -930 {
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lab=RRSSTT}
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N 480 -910 630 -910 {
|
||||
lab=CCKK}
|
||||
N 480 -890 630 -890 {
|
||||
lab=AA}
|
||||
lab=AA[3:0]}
|
||||
N 480 -870 630 -870 {
|
||||
lab=BB}
|
||||
N 480 -830 510 -830 {
|
||||
|
|
@ -58,29 +50,29 @@ lab=RRSSTT}
|
|||
N 480 -1370 630 -1370 {
|
||||
lab=CCKK}
|
||||
N 480 -1350 630 -1350 {
|
||||
lab=AA}
|
||||
lab=AA[3:0]}
|
||||
N 480 -1330 630 -1330 {
|
||||
lab=BB}
|
||||
N 480 -720 660 -720 {
|
||||
lab=RRSSTT}
|
||||
lab=#net1}
|
||||
N 480 -700 660 -700 {
|
||||
lab=CCKK}
|
||||
lab=#net2}
|
||||
N 480 -680 660 -680 {
|
||||
lab=AA}
|
||||
lab=#net3}
|
||||
N 480 -660 660 -660 {
|
||||
lab=BB}
|
||||
lab=#net4}
|
||||
N 480 -620 510 -620 {
|
||||
lab=ZZ7}
|
||||
N 630 -620 660 -620 {
|
||||
lab=ZZ8}
|
||||
N 960 -720 1080 -720 {
|
||||
lab=RRSSTT}
|
||||
lab=#net5}
|
||||
N 960 -700 1080 -700 {
|
||||
lab=CCKK}
|
||||
lab=#net6}
|
||||
N 960 -680 1080 -680 {
|
||||
lab=AA}
|
||||
lab=#net7}
|
||||
N 960 -660 1080 -660 {
|
||||
lab=BB}
|
||||
lab=#net8}
|
||||
N 1380 -620 1410 -620 {
|
||||
lab=ZZ9}
|
||||
N 480 -510 660 -510 {
|
||||
|
|
@ -95,136 +87,215 @@ N 480 -410 510 -410 {
|
|||
lab=ZZ12}
|
||||
N 630 -410 660 -410 {
|
||||
lab=ZZ11}
|
||||
N 960 -510 1080 -510 {
|
||||
lab=#net13}
|
||||
N 960 -490 1080 -490 {
|
||||
lab=#net14}
|
||||
N 960 -470 1080 -470 {
|
||||
lab=#net15}
|
||||
N 960 -450 1080 -450 {
|
||||
lab=#net16}
|
||||
N 1380 -410 1410 -410 {
|
||||
N 1260 -410 1290 -410 {
|
||||
lab=ZZ10}
|
||||
N 1520 -990 1550 -990 {
|
||||
lab=ZZ13}
|
||||
N 1170 -1090 1220 -1090 {
|
||||
lab=RRSSTT}
|
||||
lab=#net13}
|
||||
N 1170 -1070 1220 -1070 {
|
||||
lab=CCKK}
|
||||
lab=#net14}
|
||||
N 1170 -1050 1220 -1050 {
|
||||
lab=AA}
|
||||
lab=#net15}
|
||||
N 1170 -1030 1220 -1030 {
|
||||
lab=BB}
|
||||
lab=#net16}
|
||||
N 1190 -1250 1220 -1250 {
|
||||
lab=ZZ14}
|
||||
N 1170 -1350 1220 -1350 {
|
||||
lab=RRSSTT}
|
||||
lab=#net17}
|
||||
N 1170 -1330 1220 -1330 {
|
||||
lab=CCKK}
|
||||
lab=#net18}
|
||||
N 1170 -1310 1220 -1310 {
|
||||
lab=AA}
|
||||
lab=#net19}
|
||||
N 1170 -1290 1220 -1290 {
|
||||
lab=BB}
|
||||
lab=#net20}
|
||||
N 480 -280 660 -280 {
|
||||
lab=#net25}
|
||||
lab=#net21}
|
||||
N 480 -260 660 -260 {
|
||||
lab=#net26}
|
||||
lab=#net22}
|
||||
N 480 -240 660 -240 {
|
||||
lab=#net27}
|
||||
lab=#net23}
|
||||
N 480 -220 660 -220 {
|
||||
lab=#net28}
|
||||
lab=#net24}
|
||||
N 480 -180 510 -180 {
|
||||
lab=ZZ17}
|
||||
N 630 -180 660 -180 {
|
||||
lab=ZZ16}
|
||||
N 960 -280 1080 -280 {
|
||||
lab=#net29}
|
||||
lab=#net25}
|
||||
N 960 -260 1080 -260 {
|
||||
lab=#net30}
|
||||
lab=#net26}
|
||||
N 960 -240 1080 -240 {
|
||||
lab=#net31}
|
||||
lab=#net27}
|
||||
N 960 -220 1080 -220 {
|
||||
lab=#net32}
|
||||
lab=#net28}
|
||||
N 1380 -180 1410 -180 {
|
||||
lab=ZZ15}
|
||||
N 10 -260 40 -260 {
|
||||
lab=#net33}
|
||||
lab=#net29}
|
||||
N 120 -260 180 -260 {
|
||||
lab=#net30}
|
||||
N 70 -450 100 -450 {
|
||||
lab=#net31}
|
||||
N 1260 -510 1440 -510 {
|
||||
lab=#net32}
|
||||
N 1260 -490 1440 -490 {
|
||||
lab=#net33}
|
||||
N 1260 -470 1440 -470 {
|
||||
lab=#net34}
|
||||
C {doublepin.sym} 1230 -670 0 0 {name=x9}
|
||||
C {doublepin.sym} 810 -670 0 1 {name=x8}
|
||||
C {doublepin.sym} 780 -880 0 0 {name=x2}
|
||||
C {lab_wire.sym} 550 -890 0 0 {name=l2 sig_type=std_logic lab=AA}
|
||||
N 1260 -450 1440 -450 {
|
||||
lab=#net35}
|
||||
N 1740 -310 1770 -310 {
|
||||
lab=ZZ18}
|
||||
N 1740 -410 1740 -310 {
|
||||
lab=ZZ18}
|
||||
N 2040 -310 2070 -310 {
|
||||
lab=ZZ19}
|
||||
N 2040 -410 2040 -310 {
|
||||
lab=ZZ19}
|
||||
N 620 -350 620 -280 {
|
||||
lab=#net21}
|
||||
N 620 -350 680 -350 {
|
||||
lab=#net21}
|
||||
N 760 -350 810 -350 {
|
||||
lab=#net36}
|
||||
N 1110 -920 1260 -920 {
|
||||
lab=RRSSTT}
|
||||
N 1110 -900 1260 -900 {
|
||||
lab=CCKK}
|
||||
N 1110 -880 1260 -880 {
|
||||
lab=AA[3:0]}
|
||||
N 1110 -860 1260 -860 {
|
||||
lab=BB}
|
||||
N 1560 -820 1590 -820 {
|
||||
lab=ZZ20}
|
||||
N 1560 -920 1760 -920 {
|
||||
lab=RRSSTT}
|
||||
N 1560 -900 1760 -900 {
|
||||
lab=CCKK}
|
||||
N 1560 -880 1760 -880 {
|
||||
lab=AA[3:0]}
|
||||
N 1560 -860 1760 -860 {
|
||||
lab=BB}
|
||||
N 1730 -820 1760 -820 {
|
||||
lab=ZZ21}
|
||||
N 2060 -880 2180 -880 {
|
||||
lab=#net37}
|
||||
N 2060 -860 2180 -860 {
|
||||
lab=#net38}
|
||||
N 2060 -900 2180 -900 {
|
||||
lab=#net39}
|
||||
N 2060 -920 2180 -920 {
|
||||
lab=#net40}
|
||||
C {doublepin.sym} 1230 -670 0 0 {name=x9
|
||||
net_name=true}
|
||||
C {doublepin.sym} 810 -670 0 1 {name=x8
|
||||
net_name=true}
|
||||
C {doublepin.sym} 780 -880 0 0 {name=x2
|
||||
net_name=true}
|
||||
C {lab_wire.sym} 550 -890 0 0 {name=l2 sig_type=std_logic lab=AA[3:0]}
|
||||
C {lab_pin.sym} 510 -830 0 1 {name=p3 lab=ZZ5}
|
||||
C {lab_pin.sym} 960 -830 0 1 {name=p5 lab=ZZ6}
|
||||
C {lab_wire.sym} 550 -930 0 0 {name=l3 sig_type=std_logic lab=RRSSTT}
|
||||
C {lab_wire.sym} 550 -910 0 0 {name=l4 sig_type=std_logic lab=CCKK}
|
||||
C {lab_wire.sym} 550 -870 0 0 {name=l5 sig_type=std_logic lab=BB}
|
||||
C {doublepin.sym} 330 -1110 0 0 {name=x3}
|
||||
C {doublepin.sym} 780 -1110 0 0 {name=x4}
|
||||
C {lab_pin.sym} 180 -1120 0 0 {name=l6 sig_type=std_logic lab=AA}
|
||||
C {doublepin.sym} 330 -1110 0 0 {name=x3
|
||||
net_name=true}
|
||||
C {doublepin.sym} 780 -1110 0 0 {name=x4
|
||||
net_name=true}
|
||||
C {lab_pin.sym} 180 -1120 0 0 {name=l6 sig_type=std_logic lab=AA[3:0]}
|
||||
C {lab_pin.sym} 510 -1060 0 1 {name=p1 lab=ZZ3}
|
||||
C {lab_pin.sym} 960 -1060 0 1 {name=p2 lab=ZZ4}
|
||||
C {lab_pin.sym} 180 -1160 0 0 {name=l7 sig_type=std_logic lab=RRSSTT}
|
||||
C {lab_pin.sym} 180 -1140 0 0 {name=l8 sig_type=std_logic lab=CCKK}
|
||||
C {lab_pin.sym} 180 -1100 0 0 {name=l9 sig_type=std_logic lab=BB}
|
||||
C {lab_pin.sym} 930 -1120 0 1 {name=l10 sig_type=std_logic lab=AA}
|
||||
C {lab_pin.sym} 930 -1120 0 1 {name=l10 sig_type=std_logic lab=AA[3:0]}
|
||||
C {lab_pin.sym} 930 -1160 0 1 {name=l11 sig_type=std_logic lab=RRSSTT}
|
||||
C {lab_pin.sym} 930 -1140 0 1 {name=l12 sig_type=std_logic lab=CCKK}
|
||||
C {lab_pin.sym} 930 -1100 0 1 {name=l13 sig_type=std_logic lab=BB}
|
||||
C {doublepin.sym} 330 -1340 0 0 {name=x5}
|
||||
C {doublepin.sym} 780 -1340 0 0 {name=x6}
|
||||
C {lab_pin.sym} 180 -1350 0 0 {name=l14 sig_type=std_logic lab=AA}
|
||||
C {doublepin.sym} 330 -1340 0 0 {name=x5
|
||||
net_name=true}
|
||||
C {doublepin.sym} 780 -1340 0 0 {name=x6
|
||||
net_name=true}
|
||||
C {lab_pin.sym} 180 -1350 0 0 {name=l14 sig_type=std_logic lab=AA[3:0]}
|
||||
C {lab_pin.sym} 510 -1290 0 1 {name=p4 lab=ZZ1}
|
||||
C {lab_pin.sym} 960 -1290 0 1 {name=p6 lab=ZZ2}
|
||||
C {lab_pin.sym} 180 -1390 0 0 {name=l15 sig_type=std_logic lab=RRSSTT}
|
||||
C {lab_pin.sym} 180 -1370 0 0 {name=l16 sig_type=std_logic lab=CCKK}
|
||||
C {lab_pin.sym} 180 -1330 0 0 {name=l17 sig_type=std_logic lab=BB}
|
||||
C {lab_pin.sym} 930 -1350 0 1 {name=l18 sig_type=std_logic lab=AA}
|
||||
C {lab_pin.sym} 930 -1350 0 1 {name=l18 sig_type=std_logic lab=AA[3:0]}
|
||||
C {lab_pin.sym} 930 -1390 0 1 {name=l19 sig_type=std_logic lab=RRSSTT}
|
||||
C {lab_pin.sym} 930 -1370 0 1 {name=l20 sig_type=std_logic lab=CCKK}
|
||||
C {lab_pin.sym} 930 -1330 0 1 {name=l21 sig_type=std_logic lab=BB}
|
||||
C {lab_wire.sym} 550 -1350 0 0 {name=l22 sig_type=std_logic lab=AA}
|
||||
C {lab_wire.sym} 550 -1350 0 0 {name=l22 sig_type=std_logic lab=AA[3:0]}
|
||||
C {lab_wire.sym} 550 -1390 0 0 {name=l23 sig_type=std_logic lab=RRSSTT}
|
||||
C {lab_wire.sym} 550 -1370 0 0 {name=l24 sig_type=std_logic lab=CCKK}
|
||||
C {lab_wire.sym} 550 -1330 0 0 {name=l25 sig_type=std_logic lab=BB}
|
||||
C {lab_pin.sym} 180 -660 0 0 {name=l33 sig_type=std_logic lab=BB}
|
||||
C {doublepin.sym} 330 -880 0 0 {name=x1}
|
||||
C {doublepin.sym} 330 -880 0 0 {name=x1
|
||||
net_name=true}
|
||||
C {lab_pin.sym} 510 -620 0 1 {name=p7 lab=ZZ7}
|
||||
C {lab_pin.sym} 630 -620 0 0 {name=p8 lab=ZZ8}
|
||||
C {lab_pin.sym} 180 -680 0 0 {name=l30 sig_type=std_logic lab=AA}
|
||||
C {lab_pin.sym} 180 -680 0 0 {name=l30 sig_type=std_logic lab=AA[3:0]}
|
||||
C {lab_pin.sym} 180 -720 0 0 {name=l31 sig_type=std_logic lab=RRSSTT}
|
||||
C {lab_pin.sym} 180 -700 0 0 {name=l32 sig_type=std_logic lab=CCKK}
|
||||
C {doublepin.sym} 330 -670 0 0 {name=x7}
|
||||
C {doublepin.sym} 330 -670 0 0 {name=x7
|
||||
net_name=true}
|
||||
C {ipin.sym} 100 -80 0 0 { name=p9 lab=RRSSTT }
|
||||
C {ipin.sym} 100 -100 0 0 { name=p10 lab=CCKK }
|
||||
C {ipin.sym} 100 -120 0 0 { name=p11 lab=BB }
|
||||
C {ipin.sym} 100 -140 0 0 { name=p12 lab=AA }
|
||||
C {opin.sym} 270 -120 0 0 { name=p13 lab=ZZ[17..1]}
|
||||
C {ipin.sym} 100 -140 0 0 { name=p12 lab=AA[3:0] }
|
||||
C {opin.sym} 270 -120 0 0 { name=p13 lab=ZZ[21..1]}
|
||||
C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"}
|
||||
C {lab_pin.sym} 1410 -620 0 1 {name=p8 lab=ZZ9}
|
||||
C {doublepin.sym} 1230 -460 0 0 {name=x10}
|
||||
C {doublepin.sym} 810 -460 0 1 {name=x11}
|
||||
C {doublepin.sym} 1110 -460 0 0 {name=x10
|
||||
net_name=true}
|
||||
C {doublepin.sym} 810 -460 0 1 {name=x11
|
||||
net_name=true}
|
||||
C {lab_pin.sym} 510 -410 0 1 {name=p7 lab=ZZ12}
|
||||
C {lab_pin.sym} 630 -410 0 0 {name=p8 lab=ZZ11}
|
||||
C {doublepin.sym} 330 -460 0 0 {name=x12}
|
||||
C {lab_pin.sym} 1410 -410 0 1 {name=p1 lab=ZZ10}
|
||||
C {doublepin.sym} 1370 -1040 0 0 {name=x13}
|
||||
C {doublepin.sym} 330 -460 0 0 {name=x12
|
||||
net_name=true}
|
||||
C {lab_pin.sym} 1290 -410 0 1 {name=p1 lab=ZZ10}
|
||||
C {doublepin.sym} 1370 -1040 0 0 {name=x13
|
||||
net_name=true}
|
||||
C {lab_pin.sym} 1550 -990 0 1 {name=p2 lab=ZZ13}
|
||||
C {lab_pin.sym} 1520 -1050 0 1 {name=l10 sig_type=std_logic lab=AA}
|
||||
C {lab_pin.sym} 1520 -1050 0 1 {name=l1 sig_type=std_logic lab=AA[3:0]}
|
||||
C {lab_pin.sym} 1520 -1090 0 1 {name=l11 sig_type=std_logic lab=RRSSTT}
|
||||
C {lab_pin.sym} 1520 -1070 0 1 {name=l12 sig_type=std_logic lab=CCKK}
|
||||
C {lab_pin.sym} 1520 -1030 0 1 {name=l13 sig_type=std_logic lab=BB}
|
||||
C {doublepin.sym} 1370 -1300 0 1 {name=x14}
|
||||
C {doublepin.sym} 1370 -1300 0 1 {name=x14
|
||||
net_name=true}
|
||||
C {lab_pin.sym} 1190 -1250 0 0 {name=p2 lab=ZZ14}
|
||||
C {lab_pin.sym} 1520 -1310 0 1 {name=l10 sig_type=std_logic lab=AA}
|
||||
C {lab_pin.sym} 1520 -1310 0 1 {name=l3 sig_type=std_logic lab=AA[3:0]}
|
||||
C {lab_pin.sym} 1520 -1350 0 1 {name=l11 sig_type=std_logic lab=RRSSTT}
|
||||
C {lab_pin.sym} 1520 -1330 0 1 {name=l12 sig_type=std_logic lab=CCKK}
|
||||
C {lab_pin.sym} 1520 -1290 0 1 {name=l13 sig_type=std_logic lab=BB}
|
||||
C {doublepin.sym} 330 -230 0 0 {name=x17}
|
||||
C {doublepin.sym} 810 -230 0 1 {name=x16}
|
||||
C {doublepin.sym} 330 -230 0 0 {name=x17[1:0]
|
||||
net_name=true}
|
||||
C {doublepin.sym} 810 -230 0 1 {name=x16[1:0]
|
||||
net_name=true}
|
||||
C {lab_pin.sym} 510 -180 0 1 {name=p7 lab=ZZ17}
|
||||
C {lab_pin.sym} 630 -180 0 0 {name=p8 lab=ZZ16}
|
||||
C {doublepin.sym} 1230 -230 0 0 {name=x15}
|
||||
C {doublepin.sym} 1230 -230 0 0 {name=x22[1:0]
|
||||
net_name=true}
|
||||
C {lab_pin.sym} 1410 -180 0 1 {name=p1 lab=ZZ15}
|
||||
C {inv_ngspice.sym} 80 -260 0 0 {name=x18 ROUT=1000}
|
||||
C {inv_ngspice.sym} 80 -260 0 0 {name=x18 ROUT=1000 net_name=true}
|
||||
C {inv_ngspice.sym} 140 -450 0 0 {name=x19 ROUT=1000 net_name=true}
|
||||
C {doublepin.sym} 1590 -460 0 0 {name=x20
|
||||
net_name=true}
|
||||
C {lab_pin.sym} 1770 -310 0 1 {name=p8 lab=ZZ18}
|
||||
C {doublepin.sym} 1890 -460 0 0 {name=x21
|
||||
net_name=true}
|
||||
C {lab_pin.sym} 2070 -310 0 1 {name=p8 lab=ZZ19}
|
||||
C {inv_ngspice.sym} 720 -350 0 0 {name=x15 ROUT=1000 net_name=true}
|
||||
C {doublepin.sym} 1410 -870 0 0 {name=x23
|
||||
net_name=true}
|
||||
C {lab_wire.sym} 1180 -880 0 0 {name=l2 sig_type=std_logic lab=AA[3:0]}
|
||||
C {lab_pin.sym} 1590 -820 0 1 {name=p5 lab=ZZ20}
|
||||
C {lab_wire.sym} 1180 -920 0 0 {name=l3 sig_type=std_logic lab=RRSSTT}
|
||||
C {lab_wire.sym} 1180 -900 0 0 {name=l4 sig_type=std_logic lab=CCKK}
|
||||
C {lab_wire.sym} 1180 -860 0 0 {name=l5 sig_type=std_logic lab=BB}
|
||||
C {doublepin.sym} 1910 -870 0 1 {name=x24
|
||||
net_name=true}
|
||||
C {lab_pin.sym} 1730 -820 0 0 {name=p5 lab=ZZ21}
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
v {xschem version=2.9.9 file_version=1.2 }
|
||||
v {xschem version=3.1.0 file_version=1.2
|
||||
}
|
||||
G {}
|
||||
K {type=subcircuit
|
||||
format="@name @pinlist @symname ROUT=@ROUT"
|
||||
|
|
@ -20,3 +21,5 @@ T {@name} 25 -22 0 0 0.2 0.2 {}
|
|||
T {Y} 7.5 -6.5 0 1 0.2 0.2 {}
|
||||
T {A} -17.5 -6.5 0 0 0.2 0.2 {}
|
||||
T {ROUT=@ROUT} -25 -42 0 0 0.2 0.2 {}
|
||||
T {@#1:net_name} -40 6.25 0 0 0.15 0.15 {layer=15}
|
||||
T {@#0:net_name} 40 6.25 0 1 0.15 0.15 {layer=15}
|
||||
|
|
|
|||
Loading…
Reference in New Issue