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wire labels: default name set to p1 instead of l1, so it will not clash with typical inductor names

This commit is contained in:
Stefan Frederik 2022-10-12 16:36:56 +02:00
parent a820cc2e3f
commit e14c8b9a11
4 changed files with 4 additions and 4 deletions
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2
src/hilight.c
View File

@ -598,7 +598,7 @@ int search(const char *tok, const char *val, int sub, int sel)
save_draw = xctx->draw_window;
xctx->draw_window=1;
#ifdef __unix__
if(regcomp(&re, val , REG_EXTENDED)) return TCL_ERROR;
if(regcomp(&re, val , REG_NOSUB | REG_EXTENDED)) return TCL_ERROR;
#endif
dbg(1, "search():val=%s\n", val);
if(!sel) {

2
xschem_library/devices/lab_pin.sym
View File

@ -3,7 +3,7 @@ v {xschem version=3.1.0 file_version=1.2
G {}
K {type=label
format="*.alias @lab"
template="name=l1 sig_type=std_logic lab=xxx"}
template="name=p1 sig_type=std_logic lab=xxx"}
V {}
S {}
E {}

2
xschem_library/devices/lab_wire.sym
View File

@ -3,7 +3,7 @@ v {xschem version=3.1.0 file_version=1.2
G {}
K {type=label
format="*.alias @lab"
template="name=l1 sig_type=std_logic lab=xxx"}
template="name=p1 sig_type=std_logic lab=xxx"}
V {}
S {}
E {}

2
xschem_library/examples/classD_amp.sch
View File

@ -405,7 +405,7 @@ C {vsource.sym} 280 -180 0 0 {name=V7 value="SIN ( 5 4 2000 0 0 0 )"
C {lab_pin.sym} 280 -130 0 0 {name=p21 lab=VSS}
C {lab_pin.sym} 280 -230 0 0 {name=p22 lab=IN}
C {parax_cap.sym} 670 -360 0 0 {name=C4 gnd=0 value=200f m=1}
C {ind.sym} 710 -920 1 0 {name=L1
C {ind.sym} 710 -920 1 0 {name=L3
m=1
value=0.03m
footprint=1206