luke
/
xschem
mirror of https://github.com/StefanSchippers/xschem.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
1,358 Commits 3 Branches 10 Tags 88 MiB
C 71.5%
Tcl 15.7%
Awk 8.2%
Roff 2%
Yacc 0.7%
Other 1.8%
Go to file
Stefan Frederik b0359d880a use sim_pinnumber for port ordering in simulation netlists and leave pinnumber for package pin position. These two collide, for example in spice port ordering vs (transistor problem) device package pinnumbers. Dont load graphs in lcc symbols 2022-10-17 12:05:54 +02:00
XSchemWin update xschemtest, more robust spice flatten.awk netlist flattener, specifically when translating expressions containing electrical nodes and parameters, all these need to be translated/substituted. 2022-10-12 01:16:23 +02:00
doc doc updates (pinnumber) 2022-10-16 23:00:19 +02:00
scconfig monospaced font in code_shown.sym 2022-08-30 15:54:18 +02:00
src use sim_pinnumber for port ordering in simulation netlists and leave pinnumber for package pin position. These two collide, for example in spice port ordering vs (transistor problem) device package pinnumbers. Dont load graphs in lcc symbols 2022-10-17 12:05:54 +02:00
tests update xschemtest hashes, uniquify allocation IDs 2022-10-16 14:21:22 +02:00
xschem_library use sim_pinnumber for port ordering in simulation netlists and leave pinnumber for package pin position. These two collide, for example in spice port ordering vs (transistor problem) device package pinnumbers. Dont load graphs in lcc symbols 2022-10-17 12:05:54 +02:00
.gitignore changed .gitignore for specific xschem files 2020-08-08 23:25:43 +02:00
AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
Changelog Update Changelog 2022-07-28 10:31:07 +02:00
INSTALL populating xschem git repo 2020-08-08 15:47:34 +02:00
LICENSE update license info 2021-07-27 16:42:54 +02:00
Makefile populating xschem git repo 2020-08-08 15:47:34 +02:00
Makefile.conf.in populating xschem git repo 2020-08-08 15:47:34 +02:00
README update license info 2021-07-27 16:42:54 +02:00
README.md Update README.md 2020-10-08 00:54:06 +02:00
README_MacOS.md added notes for MacOS 'Big Sur' builds. 2021-09-26 13:24:51 +02:00
config.h.in remove all xrender and all xcb code, remove detection as well. Fix a couple of potentially uninitialized variables 2022-01-19 00:49:46 +01:00
configure populating xschem git repo 2020-08-08 15:47:34 +02:00

README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions