add test_extracted_netlist circuit example

This commit is contained in:
Stefan Frederik 2022-02-18 15:11:44 +01:00
parent cca3f1cc05
commit 1d8fe237ce
10 changed files with 2277 additions and 1941 deletions

File diff suppressed because it is too large Load Diff

View File

@ -593,6 +593,9 @@
<Component Id="cmp1CB191EAD2BF728BA3BBB51212CD9247" Guid="{69C694D5-5DD4-4A22-994C-6A3580F442B4}">
<File Id="fil58F186B07EB593663AEED328B4D974F3" KeyPath="yes" Source="$(var.xschemLibrarySrcDir)\examples\test_doublepin.sch" />
</Component>
<Component Id="cmp67FF7D4EB6E699EEC0A31BF183FA828E" Guid="{7561011E-54C6-42BA-84F5-05F7DAB21752}">
<File Id="fil2F44BBFE88AADBFBEF5B4B523B53C26C" KeyPath="yes" Source="$(var.xschemLibrarySrcDir)\examples\test_doublepin.sym" />
</Component>
<Component Id="cmp77E0F6C53A43FB1A2E8231AA49C7A604" Guid="{62C5CBE3-D841-4D0E-A076-75414096A2DA}">
<File Id="fil44DEAF0637B5696172643A0ED1297267" KeyPath="yes" Source="$(var.xschemLibrarySrcDir)\examples\test_lm324.sch" />
</Component>
@ -4858,6 +4861,9 @@
<Component Id="cmp5547F9E68EDF6E118AD8BA716982ADB3" Guid="{611CA23B-3370-4598-9B95-BC87743F8625}">
<File Id="filB378B505E858540E93C9E9C4CFE9CFBD" KeyPath="yes" Source="$(var.xschemLibrarySrcDir)\ngspice\delta_sigma.sch" />
</Component>
<Component Id="cmpF330B01CCAB5F41A8CDCA56806CAF501" Guid="{EA4AAF7C-ECCE-4FC7-931D-F32CAE6B9637}">
<File Id="fil64ADF324BB301500D7BF472906CEF9AB" KeyPath="yes" Source="$(var.xschemLibrarySrcDir)\ngspice\delta_sigma.sym" />
</Component>
<Component Id="cmp70D8EDA5E2D1C25F9EF091255B0E5459" Guid="{55E78524-0BA3-4BAB-B7D8-B046B29D2755}">
<File Id="filF63EED06EAB648574272CEC9437B4D1B" KeyPath="yes" Source="$(var.xschemLibrarySrcDir)\ngspice\flip_flop_ngspice.sch" />
</Component>
@ -4936,6 +4942,9 @@
<Component Id="cmp48D7195380E19ED4C8F932A9689DD5B1" Guid="{026D6F37-AB74-4D58-8D8F-F56CC5C049C5}">
<File Id="fil3AC786059B4ECA2A7AF7C9F680C7A704" KeyPath="yes" Source="$(var.xschemLibrarySrcDir)\ngspice\solar_panel.sch" />
</Component>
<Component Id="cmpAC42AF41D0318B819EC0508F6B8D20CB" Guid="{6A5E4FD1-DE4F-4B16-91A5-EFD669E965FE}">
<File Id="filD4C42E0F4C6F3676046F42C8BB6943CA" KeyPath="yes" Source="$(var.xschemLibrarySrcDir)\ngspice\solar_panel.sym" />
</Component>
<Component Id="cmp77356AD341ED858C86F7395F40A57F7A" Guid="{68E2DA53-D106-4E05-914D-6FB52DC02E50}">
<File Id="fil7FF75E4833B9DD8C894A0995CF34BB96" KeyPath="yes" Source="$(var.xschemLibrarySrcDir)\ngspice\solar_panel_xyce.sch" />
</Component>
@ -5575,6 +5584,7 @@
<ComponentRef Id="cmp0F886DAEE595168D462438D292C5868D" />
<ComponentRef Id="cmpAEF56BDB09D122243A6EAE07734B3F38" />
<ComponentRef Id="cmp1CB191EAD2BF728BA3BBB51212CD9247" />
<ComponentRef Id="cmp67FF7D4EB6E699EEC0A31BF183FA828E" />
<ComponentRef Id="cmp77E0F6C53A43FB1A2E8231AA49C7A604" />
<ComponentRef Id="cmp4B4D8B4C4B196D864383F4138BBA8B2D" />
<ComponentRef Id="cmp7BBFD4FFD4BD205783E8852433FC5873" />
@ -6994,6 +7004,7 @@
<ComponentRef Id="cmp5939E8B864B2C6BA45646DF8566FDC96" />
<ComponentRef Id="cmp62F93427FE69E5A06D66F6A8CEAEDF3E" />
<ComponentRef Id="cmp5547F9E68EDF6E118AD8BA716982ADB3" />
<ComponentRef Id="cmpF330B01CCAB5F41A8CDCA56806CAF501" />
<ComponentRef Id="cmp70D8EDA5E2D1C25F9EF091255B0E5459" />
<ComponentRef Id="cmpBAEAE74C45E5CA5F74FAB388199B41B6" />
<ComponentRef Id="cmpE6EFB433893F0DC06DEFB3CB09F50A90" />
@ -7020,6 +7031,7 @@
<ComponentRef Id="cmpCBC7FB80FEAF230C77237A28A4B323F6" />
<ComponentRef Id="cmp0F9FE65C90437BA6A6262ADD2D07CC18" />
<ComponentRef Id="cmp48D7195380E19ED4C8F932A9689DD5B1" />
<ComponentRef Id="cmpAC42AF41D0318B819EC0508F6B8D20CB" />
<ComponentRef Id="cmp77356AD341ED858C86F7395F40A57F7A" />
<ComponentRef Id="cmpDB6B5CBFE445584C13D50BDB01BBE11A" />
<ComponentRef Id="cmpC7926C63F014277EC36E893A1F3696D4" />

View File

@ -124,7 +124,6 @@ void print_image()
#if HAS_CAIRO==1
void set_cairo_color(int layer)
{
#ifdef __unix__
cairo_set_source_rgb(xctx->cairo_ctx,
(double)xctx->xcolor_array[layer].red/65535.0,
(double)xctx->xcolor_array[layer].green/65535.0,
@ -133,10 +132,6 @@ void set_cairo_color(int layer)
(double)xctx->xcolor_array[layer].red/65535.0,
(double)xctx->xcolor_array[layer].green/65535.0,
(double)xctx->xcolor_array[layer].blue/65535.0);
#else /* temporary until I get find_best_color to work on Windows */
cairo_set_source_rgb(xctx->cairo_ctx, 1, 0, 0);
cairo_set_source_rgb(xctx->cairo_save_ctx, 1, 0, 0);
#endif
}
/* remember to call cairo_restore(xctx->cairo_ctx) when done !! */

View File

@ -220,20 +220,10 @@ unsigned int find_best_color(char colorname[])
/* dbg(1, "find_best_color() start: %g\n", timer(1)); */
#ifdef __unix__
if( XAllocNamedColor(display, colormap, colorname, &xcolor_exact, &xcolor) ==0 )
#else
Tk_Window mainwindow = Tk_MainWindow(interp);
XColor* xc = Tk_GetColor(interp, mainwindow, colorname);
if (XAllocColor(display, colormap, xc) == 0)
#endif
{
for(i=0;i<=255;i++) {
xctx->xcolor_array[i].pixel=i;
#ifdef __unix__
XQueryColor(display, colormap, xctx->xcolor_array+i);
#else
xcolor = *xc;
XQueryColors(display, colormap, xc, i);
#endif
}
/* debug ... */
dbg(2, "find_best_color(): Server failed to allocate requested color, finding substitute\n");
@ -255,14 +245,16 @@ unsigned int find_best_color(char colorname[])
else
{
/*XLookupColor(display, colormap, colorname, &xcolor_exact, &xcolor); */
#ifdef __unix__
idx = xcolor.pixel;
#else
idx = xc->pixel;
#endif
}
/* dbg(1, "find_best_color() return: %g\n", timer(1)); */
return idx;
#else
Tk_Window mainwindow = Tk_MainWindow(interp);
XColor *xc = Tk_GetColor(interp, mainwindow, colorname);
/* if (XAllocColor(display, colormap, xc)) return(xc->pixel); */
return xc->pixel;
#endif
}
@ -780,8 +772,14 @@ int build_colors(double dim, double dim_bg)
XSetForeground(display, xctx->gcstipple[i], xctx->color_index[i]);
}
for(i=0;i<cadlayers;i++) {
#ifdef __unix__
XLookupColor(display, colormap, xctx->color_array[i], &xcolor_exact, &xcolor);
xctx->xcolor_array[i] = xcolor;
#else
Tk_Window mainwindow = Tk_MainWindow(interp);
XColor *xc = Tk_GetColor(interp, mainwindow, xctx->color_array[i]);
xctx->xcolor_array[i] = *xc;
#endif
}
tcleval("reconfigure_layers_menu");
return 0; /* success */
@ -1541,7 +1539,6 @@ void resetcairo(int create, int clear, int force_or_resize)
HWND hwnd = Tk_GetHWND(xctx->window);
HDC dc = GetDC(hwnd);
xctx->cairo_save_sfc = cairo_win32_surface_create(dc);
cairo_surface_set_device_scale(xctx->cairo_save_sfc, 1, 1);
#endif
if(cairo_surface_status(xctx->cairo_save_sfc)!=CAIRO_STATUS_SUCCESS) {
fprintf(errfp, "ERROR: invalid cairo xcb surface\n");
@ -1563,7 +1560,6 @@ void resetcairo(int create, int clear, int force_or_resize)
xctx->xrect[0].width, xctx->xrect[0].height);
#else
xctx->cairo_sfc = cairo_win32_surface_create(dc);
cairo_surface_set_device_scale(xctx->cairo_sfc, 1, 1);
#endif
if(cairo_surface_status(xctx->cairo_sfc)!=CAIRO_STATUS_SUCCESS) {
fprintf(errfp, "ERROR: invalid cairo surface\n");

View File

@ -44,7 +44,7 @@ A 7 884.1666666666666 -210 39.58991173406564 210.3432488842396 198.9246444160511
P 1 10 880 -490 870 -550 950 -530 910 -510 940 -480 920 -480 910 -460 890 -500 880 -480 880 -490 {dash=3}
P 4 6 830 -470 830 -560 820 -510 820 -550 810 -520 810 -490 {}
P 15 11 870 -520 880 -560 900 -530 910 -550 920 -520 940 -530 920 -490 890 -500 860 -480 840 -530 870 -520 {fill=true}
T {Welcome to XSCHEM!} 110 -1020 0 0 1 1 {layer=5}
T {Welcome to XSCHEM!} 110 -1060 0 0 1 1 {layer=5}
T {This is a test schematic window
On the left you see some sample circuits. You may descend into any
@ -52,7 +52,7 @@ of these by selecting one with a left mouse button click and
pressing the 'e' key, or by menu 'Edit -> Push Schematic'.
You can return here after descending into a schematic by hitting
'<Ctrl>-e' or by menu 'Edit -> Pop'.
} 60 -950 0 0 0.4 0.4 {}
} 60 -990 0 0 0.4 0.4 {}
T {Lines} 960 -680 0 0 0.6 0.6 {layer=4}
T {Rectangles} 960 -620 0 0 0.6 0.6 {layer=4}
T {Polygons} 960 -530 0 0 0.6 0.6 {layer=4}
@ -88,16 +88,16 @@ N 880 -430 910 -420 {lab=#net1}
N 380 -370 640 -370 {lab=BUS[4:0]}
N 510 -460 510 -380 {lab=BUS[1]}
N 410 -420 410 -380 {lab=BUS[2]}
C {poweramp.sym} 480 -650 0 0 {name=x1
C {poweramp.sym} 480 -690 0 0 {name=x1
tclcommand="xschem descend"}
C {tesla.sym} 160 -530 0 0 {name=x2}
C {test_ne555.sym} 160 -490 0 0 {name=x3}
C {test_lm324.sym} 160 -450 0 0 {name=x4}
C {osc.sym} 160 -570 0 0 {name=x5}
C {tesla.sym} 160 -570 0 0 {name=x2}
C {test_ne555.sym} 160 -530 0 0 {name=x3}
C {test_lm324.sym} 160 -490 0 0 {name=x4}
C {osc.sym} 160 -610 0 0 {name=x5}
C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"}
C {cmos_example.sym} 160 -610 0 0 {name=x6}
C {greycnt.sym} 160 -650 0 0 {name=x8}
C {loading.sym} 160 -690 0 0 {name=x9}
C {cmos_example.sym} 160 -650 0 0 {name=x6}
C {greycnt.sym} 160 -690 0 0 {name=x8}
C {loading.sym} 160 -730 0 0 {name=x9}
C {inv_bsource.sym} 880 -320 0 0 {name=B1 TABLE="1.4 3.0 1.6 0.0"}
C {launcher.sym} 460 -160 0 0 {name=h1
descr="XSCHEM ON REPO.HU"
@ -114,17 +114,17 @@ url="$\{XSCHEM_SHAREDIR\}/../doc/xschem/index.html"
program=x-www-browser
}
C {rlc.sym} 160 -730 0 0 {name=x0}
C {rlc.sym} 160 -770 0 0 {name=x0}
C {lab_pin.sym} 640 -370 0 1 {name=l2 sig_type=std_logic lab=BUS[4:0]}
C {bus_connect.sym} 500 -370 0 0 {name=l3 lab=BUS[1]}
C {bus_connect_nolab.sym} 400 -370 0 0 {name=r1}
C {lab_pin.sym} 410 -420 3 1 {name=l4 sig_type=std_logic lab=BUS[2]}
C {LCC_instances.sym} 160 -410 0 0 {name=x7}
C {test_backannotated_subckt.sym} 160 -370 0 0 {name=x10}
C {plot_manipulation.sym} 160 -330 0 0 {name=x11}
C {logic_test.sym} 160 -290 0 0 {name=x12}
C {simulate_ff.sym} 160 -250 0 0 {name=x13}
C {test_mos_verilog.sym} 160 -210 0 0 {name=x14}
C {LCC_instances.sym} 160 -450 0 0 {name=x7}
C {test_backannotated_subckt.sym} 160 -410 0 0 {name=x10}
C {plot_manipulation.sym} 160 -370 0 0 {name=x11}
C {logic_test.sym} 160 -330 0 0 {name=x12}
C {simulate_ff.sym} 160 -290 0 0 {name=x13}
C {test_mos_verilog.sym} 160 -250 0 0 {name=x14}
C {launcher.sym} 1265 -225 0 0 {name=h5
descr=" Ctrl-Left-Click to load/
unload waveforms"
@ -1457,12 +1457,14 @@ xwtAgA9ve8fHC0Dod8blIpQLQJBdgRgxavQ/AAAAgEslwD6d7SiMdxwqP41maeirFRxABH/Rb+tVM0DO
cwtAyKwqggMC8z8AAABAXz/APixDHOviNio/cIyWTt0GHEAHmaX3NW0zQHJvU5F/bTNA3V5CW3kqoL85tJeeXUIJQIB/waNeQglAcFfF8JIdC0DY7tjwBPjxPwAAALCc
UsA+"
}
C {test_ac.sym} 160 -170 0 0 {name=x15}
C {test_ac_xyce.sym} 160 -130 0 0 {name=x16}
C {rom8k.sym} 480 -690 0 0 {name=x17}
C {poweramp_xyce.sym} 480 -610 0 0 {name=x18
C {test_ac.sym} 160 -210 0 0 {name=x15}
C {test_ac_xyce.sym} 160 -170 0 0 {name=x16}
C {rom8k.sym} 480 -730 0 0 {name=x17}
C {poweramp_xyce.sym} 480 -650 0 0 {name=x18
tclcommand="xschem descend"}
C {test_doublepin.sym} 160 -130 0 0 {name=x19}
C {classD_amp.sym} 480 -770 0 0 {name=x20}
C {delta_sigma.sym} 480 -610 0 0 {name=x21}
C {solar_panel.sym} 480 -570 0 0 {name=x22}
C {test_extracted_netlist.sym} 160 -90 0 0 {name=x23
tclcommand="xschem descend"}
C {test_doublepin.sym} 160 -90 0 0 {name=x19}
C {classD_amp.sym} 480 -730 0 0 {name=x20}
C {delta_sigma.sym} 480 -570 0 0 {name=x21}
C {solar_panel.sym} 480 -530 0 0 {name=x22}

View File

@ -0,0 +1,82 @@
v {xschem version=3.0.0 file_version=1.2 }
G {}
K {}
V {}
S {xm2 net1 GB SB irf540 m=1
R7 GB SB 190 m=1
xm1 VPP GA SA irf540 m=1
R0 GA SA 190 m=1
R2 VPP E2 50 m=1
R3 VBOOST E1 50 m=1
Q5 C5 PLUS E9 q2n2222 area=1 m=1
Q4 net8 net2 E4 q2n2907p area=1 m=1
R9 VBOOST E4 50 m=1
Q6 C6 C2 net5 q2n2907p area=1 m=1
R4 VPP E6 50 m=1
vd OUTI net1 0
.save i(vd)
vu SA OUTI 0
.save i(vu)
Q1 net2 net2 E1 q2n2907p area=1 m=1
Q2 C2 C2 net4 q2n2907p area=1 m=1
Q9 C9 MINUS E9 q2n2222 area=1 m=1
R11 GB net6 1300 m=1
Q8 C8 VSS E8 q2n2907p area=1 m=1
C12 VBOOST net3 40u m=1
D0 VPP VBOOST d1n4148 area=1
R18 net3 OUTI 200 m=1
D1 VPP VBOOST d1n758
R14 B1 net7 4k m=1
Q11 GA B1 E11 q2n2907p area=1 m=1
R15 VBOOST B1 4k m=1
R5 E9 net9 120 m=1
R6 net9 net10 120 m=1
D2 VSS B3 d1n755
Q3 C3 B3 E3 q2n2222 area=1 m=1
R1 VPP B3 10k m=1
R10 E3 VSS 170 m=1
C3 B3 VSS 100n m=1
R12 C6 E8 1300 m=1
R13 C2 C9 300 m=1
Q7 C7 C9 C5 q2n2222 area=1 m=1
v0 SB VNN 0
.save i(v0)
v1 E6 net5 0
.save i(v1)
v2 E2 net4 0
.save i(v2)
v3 net10 C3 0
.save i(v3)
v4 C8 net6 0
.save i(v4)
v5 net7 OUTI 0
.save i(v5)
v6 net2 C7 0
.save i(v6)
v7 net8 E11 0
.save i(v7)
.save v(gb)
.save v(sb)
.save v(ga)
.save v(sa)
v8 OUTI OUT 0
.save i(v8)
.save v(ga)
.save v(gb)
.save v(c2)
.save v(net2)
.save v(c7)
.save v(vboost)
.save v(outi)}
E {}
T {The netlist is saved in the global
schematic attribute.
To see the netlist press 'q' (with no
selected items) or menu Properties->Edit} 130 -460 0 0 0.4 0.4 {}
C {ipin.sym} 140 -190 0 0 {name=p0 lab=PLUS}
C {ipin.sym} 140 -150 0 0 {name=p2 lab=VPP}
C {ipin.sym} 140 -130 0 0 {name=p3 lab=VNN}
C {title.sym} 160 -30 0 0 {name=l2 author="Stefan Schippers"}
C {opin.sym} 210 -160 0 0 {name=p5 lab=OUT}
C {ipin.sym} 140 -210 0 0 {name=p1 lab=MINUS}
C {ipin.sym} 140 -170 0 0 {name=p4 lab=VSS}

View File

@ -0,0 +1,34 @@
v {xschem version=3.0.0 file_version=1.2 }
G {}
K {type=subcircuit
format="@name @pinlist @symname"
template="name=x1"
net_name=true
}
V {}
S {}
E {}
L 4 -130 -50 130 -50 {}
L 4 -130 50 130 50 {}
L 4 -130 -50 -130 50 {}
L 4 130 -50 130 50 {}
L 4 -150 -40 -130 -40 {}
L 4 -150 -20 -130 -20 {}
L 4 -150 0 -130 0 {}
L 4 130 -40 150 -40 {}
L 4 -150 20 -130 20 {}
L 4 -150 40 -130 40 {}
B 5 -152.5 -42.5 -147.5 -37.5 {name=MINUS dir=in }
B 5 -152.5 -22.5 -147.5 -17.5 {name=PLUS dir=in }
B 5 -152.5 -2.5 -147.5 2.5 {name=VSS dir=in }
B 5 147.5 -42.5 152.5 -37.5 {name=OUT dir=out }
B 5 -152.5 17.5 -147.5 22.5 {name=VPP dir=in }
B 5 -152.5 37.5 -147.5 42.5 {name=VNN dir=in }
T {@symname} -100.5 -6 0 0 0.3 0.3 {}
T {@name} 135 -62 0 0 0.2 0.2 {}
T {MINUS} -125 -44 0 0 0.2 0.2 {}
T {PLUS} -125 -24 0 0 0.2 0.2 {}
T {VSS} -125 -4 0 0 0.2 0.2 {}
T {OUT} 125 -44 0 1 0.2 0.2 {}
T {VPP} -125 16 0 0 0.2 0.2 {}
T {VNN} -125 36 0 0 0.2 0.2 {}

View File

@ -0,0 +1,184 @@
v {xschem version=3.0.0 file_version=1.2 }
G {}
K {}
V {}
S {}
E {}
B 2 840 -490 1640 -90 {flags=graph
y1=-29
y2=41
ypos1=0
ypos2=2
divy=5
subdivy=1
unity=1
x1=0
x2=0.0004
divx=5
subdivx=1
dataset=0
unitx=u
color="7 8"
node="out
in"}
T {actual value
50u} 270 -580 0 0 0.4 0.4 {}
T {Example using a symbol with an extracted schematic} 660 -1180 0 0 1 1 {}
N 350 -920 350 -900 {
lab=MINUS}
N 290 -280 290 -260 {lab=#net1}
N 290 -140 290 -120 {lab=#net2}
N 480 -130 480 -120 {lab=VNN}
N 480 -200 480 -190 {lab=VSS}
N 290 -120 320 -120 {lab=#net2}
N 290 -280 320 -280 {lab=#net1}
N 480 -200 490 -200 {lab=VSS}
N 460 -280 490 -280 {lab=VPP}
N 460 -120 480 -120 {lab=VNN}
N 460 -200 480 -200 {lab=VSS}
N 490 -280 530 -280 {lab=VPP}
N 480 -120 530 -120 {lab=VNN}
N 490 -200 530 -200 {lab=VSS}
N 490 -210 490 -200 { lab=VSS}
N 490 -280 490 -270 { lab=VPP}
N 380 -280 400 -280 {lab=#net3}
N 380 -120 400 -120 {lab=#net4}
N 290 -200 400 -200 {lab=#net5}
N 660 -210 660 -190 {
lab=VSS}
N 920 -1070 920 -920 {
lab=OUT}
N 350 -1070 920 -1070 {
lab=OUT}
N 350 -1070 350 -1000 {
lab=OUT}
N 350 -920 620 -920 {
lab=MINUS}
N 550 -900 620 -900 {
lab=PLUS}
N 550 -900 550 -510 {
lab=PLUS}
N 920 -920 1060 -920 {
lab=OUT}
N 30 -390 30 -330 {
lab=VSS}
N 460 -690 460 -670 {lab=VPP}
N 480 -510 480 -480 {lab=PLUS}
N 480 -420 480 -400 {lab=VSS}
N 460 -510 480 -510 {lab=PLUS}
N 400 -510 460 -510 {lab=PLUS}
N 460 -610 460 -510 { lab=PLUS}
N 350 -940 350 -920 {
lab=MINUS}
N 350 -780 350 -750 {
lab=VSS}
N 480 -510 550 -510 {
lab=PLUS}
N 30 -510 340 -510 {
lab=IN}
N 490 -1030 490 -1010 {lab=VPP}
N 490 -950 490 -940 { lab=MINUS}
N 490 -940 490 -920 { lab=MINUS}
N 1030 -920 1030 -850 {
lab=OUT}
N 1030 -790 1030 -760 {
lab=VSS}
N 30 -510 30 -450 {
lab=IN}
C {code.sym} 20 -190 0 0 {name=STIMULI
only_toplevel=true
tclcommand="xschem edit_vi_prop"
value=".include \\"models_poweramp.txt\\"
.control
save all
op
write test_extracted_netlist.raw
set appendwrite
tran 100n 400u
* .FOUR 20k v(outm,outp)
* .probe i(*)
write test_extracted_netlist.raw
.endc
"}
C {title.sym} 160 -30 0 0 {name=l2 author="Stefan Schippers"}
C {lab_wire.sym} 620 -920 0 0 {name=l1 lab=MINUS}
C {lab_pin.sym} 620 -880 0 0 {name=p3 lab=VSS}
C {lab_pin.sym} 1060 -920 0 1 {name=p4 lab=OUT}
C {lab_pin.sym} 620 -860 0 0 {name=p5 lab=VPP}
C {lab_pin.sym} 620 -840 0 0 {name=p6 lab=VNN}
C {mos_power_ampli_extracted.sym} 770 -880 0 0 {name=x2}
C {res.sym} 350 -870 0 0 {name=R1
value=100k
footprint=1206
device=resistor
m=1}
C {res.sym} 350 -970 0 0 {name=R2
value=100k
footprint=1206
device=resistor
m=1}
C {vsource.sym} 290 -230 0 0 {name=VPP value="dc 50"}
C {vsource.sym} 290 -170 0 0 {name=VNN value="dc 50"}
C {lab_pin.sym} 530 -280 0 1 {name=p7 lab=VPP}
C {lab_pin.sym} 530 -120 0 1 {name=p8 lab=VNN}
C {lab_pin.sym} 530 -200 0 1 {name=p9 lab=VSS}
C {capa.sym} 480 -160 0 0 {name=C3 m=1 value="100u"}
C {res.sym} 350 -280 1 1 {name=R11 m=1 value=0.3}
C {res.sym} 350 -120 1 1 {name=R9 m=1 value=0.3}
C {ammeter.sym} 430 -280 3 0 {name=vcurrvpp net_name=true current=0.54}
C {ammeter.sym} 430 -120 3 0 {name=vcurrvnn net_name=true current=-0.4526}
C {ammeter.sym} 430 -200 3 0 {name=vcurrvss net_name=true current=-0.08742}
C {ngspice_probe.sym} 370 -200 0 1 {name=p34}
C {capa.sym} 490 -240 0 0 {name=C2 m=1 value="100u"}
C {ngspice_probe.sym} 290 -280 0 1 {name=p35}
C {ngspice_probe.sym} 290 -120 0 1 {name=p36}
C {ngspice_probe.sym} 530 -200 0 0 {name=p37}
C {spice_probe.sym} 520 -280 0 0 {name=p45 analysis=tran voltage=49.84}
C {spice_probe.sym} 520 -120 0 0 {name=p46 analysis=tran voltage=-49.86}
C {vsource.sym} 660 -160 0 0 {name=VVSS value=0}
C {lab_pin.sym} 660 -210 0 1 {name=p10 lab=VSS}
C {lab_pin.sym} 660 -130 0 1 {name=p11 lab=0}
C {lab_pin.sym} 350 -750 0 1 {name=p12 lab=VSS}
C {vsource.sym} 30 -420 0 0 {name=VIN value="pwl
+ 0 0 100u 0
+ 110u 10 200u 10
+ 210u 0 300u 0
+ 310u -10"
}
C {lab_pin.sym} 30 -330 0 1 {name=p1 lab=VSS}
C {spice_probe.sym} 970 -920 0 0 {name=p2 analysis=tran voltage=-49.86}
C {spice_probe.sym} 370 -920 0 0 {name=p13 analysis=tran voltage=-49.86}
C {spice_probe.sym} 120 -510 0 0 {name=p14 analysis=tran voltage=-49.86}
C {lab_wire.sym} 620 -900 0 0 {name=l3 lab=PLUS}
C {launcher.sym} 905 -535 0 0 {name=h5
descr="Select arrow and
Ctrl-Left-Click to load/unload waveforms"
tclcommand="
xschem raw_read $netlist_dir/[file tail [file rootname [xschem get current_name]]].raw
"
}
C {res.sym} 460 -640 0 1 {name=R4
value=100k
footprint=1206
device=resistor
m=1}
C {lab_pin.sym} 460 -690 0 0 {name=p18 lab=VPP}
C {res.sym} 480 -450 0 1 {name=R5
value=100k
footprint=1206
device=resistor
m=1}
C {lab_pin.sym} 480 -400 0 0 {name=p15 lab=VSS}
C {capa.sym} 370 -510 1 0 {name=C1 m=1 value="50u"}
C {capa.sym} 350 -810 0 0 {name=C4 m=1 value="50u"}
C {lab_wire.sym} 210 -510 0 0 {name=l4 lab=IN}
C {res.sym} 490 -980 0 1 {name=R13 m=1 value=100k}
C {lab_pin.sym} 490 -1030 0 0 {name=p16 lab=VPP}
C {res.sym} 1030 -820 0 0 {name=RLOAD
value=4
footprint=1206
device=resistor
m=1}
C {lab_pin.sym} 1030 -760 0 0 {name=p17 lab=VSS}

View File

@ -0,0 +1,15 @@
v {xschem version=2.9.9 file_version=1.2 }
G {}
K {type=subcircuit
format="@name @pinlist @symname"
verilog_stop=true
template="name=x1"}
V {}
S {}
E {}
L 4 -130 -10 130 -10 {}
L 4 -130 10 130 10 {}
L 4 -130 -10 -130 10 {}
L 4 130 -10 130 10 {}
T {@symname} -58.5 -6 0 0 0.3 0.3 {}
T {@name} 135 -22 0 0 0.2 0.2 {}

File diff suppressed because one or more lines are too long