annotation of voltage and currents in (nested) LCC instances
This commit is contained in:
Stefan Frederik
parent
0e6c35f598
commit
91ba5fd1d3
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@ -52,7 +52,7 @@ xinit.c \
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| sort -n \
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| awk '{
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if(n>0 && $1 <= prev) print ">>>>>>>>>>> ERROR >>>>>>>>> " $0
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else if(n++>0 && $1 != prev+1) {
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else if(n>0 && $1 != prev+1) {
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if($1-1 > prev+1)
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print ">>>>>>>>>>> FREE >>>>>>>>> " prev+1 ":" $1-1
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else
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@ -60,6 +60,7 @@ xinit.c \
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print
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} else print
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n++
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prev = $1
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}
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END{
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51
src/save.c
51
src/save.c
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@ -2784,7 +2784,7 @@ int load_sym_def(const char *name, FILE *embed_fd)
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symbols = xctx->symbols;
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dbg(1, "l_s_d(): recursion_counter=%d, name=%s\n", recursion_counter, name);
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recursion_counter++;
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dbg(1, "l_s_d(): name=%s\n", name);
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dbg(1, "l_s_d(): loading name=%s\n", name);
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lcc=NULL;
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my_realloc(647, &lcc, (level + 1) * sizeof(Lcc));
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max_level = level + 1;
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@ -3068,7 +3068,7 @@ int load_sym_def(const char *name, FILE *embed_fd)
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tt[i].txt_ptr=NULL;
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tt[i].font=NULL;
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load_ascii_string(&tt[i].txt_ptr, lcc[level].fd);
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dbg(1, "l_s_d(): txt1: tt[i].txt_ptr=%s, i=%d\n", tt[i].txt_ptr, i);
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dbg(1, "l_s_d(): txt1: level=%d tt[i].txt_ptr=%s, i=%d\n", level, tt[i].txt_ptr, i);
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if(fscanf(lcc[level].fd, "%lf %lf %hd %hd %lf %lf ",&tt[i].x0, &tt[i].y0, &tt[i].rot,
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&tt[i].flip, &tt[i].xscale, &tt[i].yscale) < 6 ) {
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fprintf(errfp,"l_s_d(): WARNING: missing fields for Text object, ignoring\n");
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@ -3081,6 +3081,49 @@ int load_sym_def(const char *name, FILE *embed_fd)
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rot = lcc[level].rot; flip = lcc[level].flip;
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if (tmp) my_strdup(651, &tt[i].txt_ptr, tmp);
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dbg(1, "l_s_d(): txt3: tt[i].txt_ptr=%s, i=%d\n", tt[i].txt_ptr, i);
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/* allow annotation inside LCC instances. */
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if(tt[i].txt_ptr && !strcmp(tt[i].txt_ptr, "@spice_get_voltage")) {
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/* prop_ptr is the attribute string of last loaded LCC component */
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const char *lab;
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size_t new_size = 0;
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char *path = NULL;
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if(level > 1) { /* add parent LCC instance names (X1, Xinv etc) */
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int i;
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for(i = 1; i <level; i++) {
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const char *instname = get_tok_value(lcc[i].prop_ptr, "name", 0);
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my_strcat(1582, &path, instname);
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my_strcat(1588, &path, ".");
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}
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}
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if(path) new_size += strlen(path);
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lab = get_tok_value(prop_ptr, "lab", 0);
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new_size += xctx->tok_size + 21; /* @spice_get_voltage(<lab>) */
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my_realloc(1587, &tt[i].txt_ptr, new_size);
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my_snprintf(tt[i].txt_ptr, new_size, "@spice_get_voltage(%s%s)", path ? path : "", lab);
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my_free(1589, &path);
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dbg(1, " --> tt[i].txt_ptr=%s\n", tt[i].txt_ptr);
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}
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if(tt[i].txt_ptr && !strcmp(tt[i].txt_ptr, "@spice_get_current")) {
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/* prop_ptr is the attribute string of last loaded LCC component */
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const char *dev;
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size_t new_size = 0;
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char *path = NULL;
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if(level > 1) { /* add parent LCC instance names (X1, Xinv etc) */
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int i;
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for(i = 1; i <level; i++) {
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const char *instname = get_tok_value(lcc[i].prop_ptr, "name", 0);
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my_strcat(1582, &path, instname);
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my_strcat(1588, &path, ".");
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}
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}
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if(path) new_size += strlen(path);
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dev = get_tok_value(prop_ptr, "name", 0);
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new_size += xctx->tok_size + 21; /* @spice_get_current(<dev>) */
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my_realloc(1587, &tt[i].txt_ptr, new_size);
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my_snprintf(tt[i].txt_ptr, new_size, "@spice_get_current(%s%s)", path ? path : "", dev);
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my_free(1589, &path);
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dbg(1, " --> tt[i].txt_ptr=%s\n", tt[i].txt_ptr);
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}
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ROTATION(rot, flip, 0.0, 0.0, tt[i].x0, tt[i].y0, rx1, ry1);
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tt[i].x0 = lcc[level].x0 + rx1; tt[i].y0 = lcc[level].y0 + ry1;
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tt[i].rot = (tt[i].rot + ((lcc[level].flip && (tt[i].rot & 1)) ?
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@ -3143,13 +3186,13 @@ int load_sym_def(const char *name, FILE *embed_fd)
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break;
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case 'C':
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load_ascii_string(&symname, lcc[level].fd);
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dbg(1, "l_s_d(): C line: symname=%s\n", symname);
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if (fscanf(lcc[level].fd, "%lf %lf %hd %hd", &inst_x0, &inst_y0, &inst_rot, &inst_flip) < 4) {
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fprintf(errfp, "l_s_d(): WARNING: missing fields for COMPONENT object, ignoring\n");
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read_line(lcc[level].fd, 0);
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continue;
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}
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load_ascii_string(&prop_ptr, lcc[level].fd);
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dbg(1, "l_s_d() component: level=%d, sym=%s, prop_ptr = %s\n", level, symname, prop_ptr);
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if(level + 1 >=CADMAXHIER) {
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fprintf(errfp, "l_s_d(): Symbol recursively instantiating symbol: max depth reached, skipping\n");
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if(has_x) tcleval("alert_ {xSymbol recursively instantiating symbol: max depth reached, skipping} {} 1");
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@ -3274,7 +3317,7 @@ int load_sym_def(const char *name, FILE *embed_fd)
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if( tag[0] == '{' ) ungetc(tag[0], lcc[level].fd);
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read_record(tag[0], lcc[level].fd, 0);
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break;
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}
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} /* switch(tag[0]) */
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/* if a 'C' line was encountered and level was incremented, rest of line must be read
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with lcc[level-1].fd file pointer */
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if(incremented_level)
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86
src/token.c
86
src/token.c
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@ -3017,11 +3017,12 @@ const char *translate(int inst, const char* s)
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if(pin_prop_ptr) net = get_tok_value(pin_prop_ptr, "lab", 0);
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if(net == NULL || net[0] == '\0') net = net_name(inst,0, &multip, 0, 0);
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len = strlen(path) + strlen(net) + 1;
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dbg(1, "net=%s\n", net);
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dbg(1, "translate() @spice_get_voltage: inst=%s\n", xctx->inst[inst].instname);
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dbg(1, " net=%s, pin_prop_ptr=%s\n", net, pin_prop_ptr);
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fqnet = my_malloc(1573, len);
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my_snprintf(fqnet, len, "%s%s", path, net);
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strtolower(fqnet);
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dbg(1, "translate(): fqnet=%s start_level=%d\n", fqnet, start_level);
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dbg(1, "translate() @spice_get_voltage: fqnet=%s start_level=%d\n", fqnet, start_level);
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idx = get_raw_index(fqnet);
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if(idx >= 0) {
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val = xctx->graph_values[idx][xctx->graph_annotate_p];
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@ -3069,12 +3070,12 @@ const char *translate(int inst, const char* s)
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n = sscanf(token + 19, "%[^)]", net);
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if(n == 1) {
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strtolower(net);
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len = strlen(path) + strlen(net) + 1;
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len = strlen(path) + strlen(xctx->inst[inst].instname) + strlen(net) + 2;
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dbg(1, "net=%s\n", net);
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fqnet = my_malloc(1548, len);
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my_snprintf(fqnet, len, "%s%s", path, net);
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my_snprintf(fqnet, len, "%s%s.%s", path, xctx->inst[inst].instname, net);
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strtolower(fqnet);
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dbg(1, "translate(): fqnet=%s start_level=%d\n", fqnet, start_level);
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dbg(1, "translate(): net=%s, fqnet=%s start_level=%d\n", net, fqnet, start_level);
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idx = get_raw_index(fqnet);
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if(idx >= 0) {
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val = xctx->graph_values[idx][xctx->graph_annotate_p];
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@ -3099,6 +3100,75 @@ const char *translate(int inst, const char* s)
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}
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}
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}
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else if(strncmp(token,"@spice_get_current(", 19)==0 )
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{
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int start_level; /* hierarchy level where waves were loaded */
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if((start_level = sch_waves_loaded()) >= 0 && xctx->graph_annotate_p>=0) {
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char *fqdev = NULL;
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const char *path = xctx->sch_path[xctx->currsch] + 1;
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char *dev = NULL;
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size_t len;
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int idx, n;
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double val;
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const char *valstr;
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tmp = strlen(token) + 1;
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if(path) {
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int skip = 0;
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/* skip path components that are above the level where raw file was loaded */
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while(*path && skip < start_level) {
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if(*path == '.') skip++;
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path++;
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}
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dev = my_malloc(1550, tmp);
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n = sscanf(token + 19, "%[^)]", dev);
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if(n == 1) {
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strtolower(dev);
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len = strlen(path) + strlen(xctx->inst[inst].instname) +
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strlen(dev) + 11; /* some extra chars for i(..) wrapper */
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dbg(1, "dev=%s\n", dev);
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fqdev = my_malloc(1556, len);
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if(!sim_is_xyce) {
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int prefix, vsource;
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char *ptr = dev;
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char *prefix_ptr = dev;
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while(*ptr) { /* since dev is something like X1.X2.V2 find last . before V */
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if(*ptr == '.') prefix_ptr = ptr + 1;
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ptr++;
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}
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prefix = prefix_ptr[0]; /* character after last '.' */
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dbg(1, "prefix=%c, path=%s\n", prefix, path);
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vsource = (prefix == 'v') || (prefix == 'e');
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if(vsource) my_snprintf(fqdev, len, "i(%c.%s%s.%s)", prefix, path, xctx->inst[inst].instname, dev);
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else my_snprintf(fqdev, len, "i(@%c.%s%s.%s)", prefix, path, xctx->inst[inst].instname, dev);
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} else {
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my_snprintf(fqdev, len, "i(%s%s.%s)", path, xctx->inst[inst].instname, dev);
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}
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strtolower(fqdev);
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dbg(1, "fqdev=%s\n", fqdev);
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idx = get_raw_index(fqdev);
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if(idx >= 0) {
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val = xctx->graph_values[idx][xctx->graph_annotate_p];
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}
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if(idx < 0) {
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valstr = "";
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xctx->tok_size = 0;
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len = 0;
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} else {
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valstr = dtoa_eng(val);
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len = xctx->tok_size;
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}
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if(len) {
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STR_ALLOC(&result, len + result_pos, &size);
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memcpy(result+result_pos, valstr, len+1);
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result_pos += len;
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}
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dbg(1, "inst %d, dev=%s, fqdev=%s idx=%d valstr=%s\n", inst, dev, fqdev, idx, valstr);
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my_free(1557, &fqdev);
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} /* if(n == 1) */
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my_free(1551, &dev);
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} /* if(path) */
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} /* if((start_level = sch_waves_loaded()) >= 0 && xctx->graph_annotate_p>=0) */
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}
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else if(strcmp(token,"@spice_get_diff_voltage")==0 )
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{
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int start_level; /* hierarchy level where waves were loaded */
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@ -3412,6 +3482,12 @@ const char *translate2(Lcc *lcc, int level, char* s)
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memcpy(result + result_pos, token, tmp + 1);
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result_pos += tmp;
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}
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else if (strncmp(token, "@spice_get_current", 18) == 0) { /* return unchanged */
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tmp = strlen(token);
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STR_ALLOC(&result, tmp + result_pos, &size);
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memcpy(result + result_pos, token, tmp + 1);
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result_pos += tmp;
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}
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else if (strcmp(token, "@symname") == 0) {
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tmp_sym_name = lcc[level].symname ? get_cell(lcc[level].symname, 0) : "";
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tmp = strlen(tmp_sym_name);
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@ -34,7 +34,7 @@ zzz"
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color="4 6 8"
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sweep="v(a)"
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dataset=-1}
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B 2 10 -930 570 -700 {flags=graph
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B 2 10 -950 570 -720 {flags=graph
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y1 = 0
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y2 = 3
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divy = 6
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@ -58,7 +58,7 @@ T {LCC schematics can be nested
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If only .sch is used there is
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no need for a .sym file at all} 840 -880 0 0 0.6 0.6 {}
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T {Select one or more graphs (and no other objects)
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and use arrow keys to zoom / pan waveforms} 20 -980 0 0 0.3 0.3 {}
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and use arrow keys to zoom / pan waveforms} 20 -1000 0 0 0.3 0.3 {}
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T {Butterfly diagram
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of a cmos latch} 620 -950 0 0 0.4 0.4 {layer=8}
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N 410 -100 410 -80 {lab=HALF}
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@ -67,12 +67,15 @@ N 410 -190 410 -160 {lab=ZZZ}
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N 420 -400 420 -380 {lab=HALF}
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N 420 -490 700 -490 {lab=ZZ}
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N 420 -490 420 -460 {lab=ZZ}
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N 700 -490 700 -240 {lab=ZZ}
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N 700 -240 1450 -240 {lab=ZZ}
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N 700 -240 1450 -240 {lab=#net1}
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N 320 -190 410 -190 {lab=ZZZ}
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N 330 -490 420 -490 {lab=ZZ}
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N 730 -860 730 -770 { lab=Z}
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N 650 -860 650 -770 { lab=A}
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N 700 -320 700 -240 {
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lab=#net1}
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N 700 -490 700 -380 {
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lab=ZZ}
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C {vsource.sym} 50 -140 0 0 {name=V1 value="pwl 0 0 1u 0 5u 3"}
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C {lab_pin.sym} 50 -170 0 0 {name=p4 lab=A}
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C {lab_pin.sym} 50 -110 0 0 {name=p5 lab=0}
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@ -158,7 +161,7 @@ C {lab_pin.sym} 410 -80 0 0 {name=p10 lab=HALF}
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C {vsource.sym} 50 -340 0 0 {name=V3 value=1.5}
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C {lab_pin.sym} 50 -370 0 0 {name=p11 lab=HALF}
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C {lab_pin.sym} 50 -310 0 0 {name=p12 lab=0}
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C {lab_pin.sym} 200 -490 0 0 {name=p13 lab=A}
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C {lab_pin.sym} 120 -490 0 0 {name=p13 lab=A}
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C {res.sym} 420 -430 0 0 {name=R2
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value=20k
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footprint=1206
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@ -166,7 +169,7 @@ device=resistor
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m=1}
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C {lab_pin.sym} 420 -380 0 0 {name=p15 lab=HALF}
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C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"}
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C {cmos_inv.sch} 140 -260 0 0 {name=Xinv WN=15u WP=45u LLN=3u LLP=3u}
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C {cmos_inv.sch} 60 -260 0 0 {name=Xinv WN=15u WP=45u LLN=3u LLP=3u}
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C {cmos_inv.sym} 280 -190 0 0 {name=Xinv2 WN=15u WP=45u LLN=3u LLP=3u}
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C {bus_keeper.sch} 1200 60 0 0 {name=Xkeeper WN_FB=3u WP_FB=5u}
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C {lab_pin.sym} 700 -490 0 1 {name=p1 lab=ZZ}
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@ -174,10 +177,11 @@ C {lab_pin.sym} 650 -770 0 0 {name=p14 lab=A}
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C {cmos_inv.sym} 690 -860 0 1 {name=Xinv3 WN=3u WP=5u LLN=3u LLP=3u}
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C {lab_pin.sym} 730 -770 0 1 {name=p2 lab=Z}
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C {cmos_inv.sym} 690 -770 0 0 {name=Xinv1 WN=3u WP=5u LLN=3u LLP=3u}
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C {launcher.sym} 85 -1015 0 0 {name=h1
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C {launcher.sym} 85 -1035 0 0 {name=h1
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descr="Select arrow and
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Ctrl-Left-Click to load/unload waveforms"
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tclcommand="
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xschem raw_read $netlist_dir/[file tail [file rootname [xschem get current_name]]].raw
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"
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}
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C {ammeter.sym} 700 -350 0 1 {name=Vmeas}
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@ -1,4 +1,5 @@
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v {xschem version=3.0.0 file_version=1.2 }
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v {xschem version=3.1.0 file_version=1.2
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}
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G {}
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K {type=subcircuit
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format="@name @pinlist @symname WN_FB=@WN_FB WP_FB=@WP_FB"
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@ -6,23 +7,24 @@ template="name=X1 WN_FB=1u WP_FB=2u"}
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V {}
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S {}
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E {}
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P 2 5 250 -880 250 -120 480 -120 480 -880 250 -880 {dash=5}
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T {@name} 250 -915 0 0 0.5 0.5 {}
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P 2 5 250 -930 250 -120 610 -120 610 -930 250 -930 {dash=5}
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T {@name} 250 -965 0 0 0.5 0.5 {}
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T {@symname} 253.75 -115 0 0 0.5 0.5 {}
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N 250 -300 300 -300 {lab=A}
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N 280 -680 300 -680 {lab=A}
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N 280 -680 280 -300 {lab=A}
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N 430 -300 450 -300 {lab=#net1}
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N 450 -680 450 -300 {lab=#net1}
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N 430 -680 450 -680 {lab=#net1}
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N 350 -500 390 -500 { lab=GND}
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N 280 -690 300 -690 {lab=A}
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N 280 -690 280 -300 {lab=A}
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N 510 -300 550 -300 {lab=Y}
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N 550 -690 550 -300 {lab=Y}
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N 510 -690 550 -690 {lab=Y}
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N 550 -240 550 -200 { lab=GND}
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C {cmos_inv.sch} 240 -70 0 0 {name=X2 WN=15u WP=45u LLN=3u LLP=3u}
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C {cmos_inv.sch} 490 -450 0 1 {name=X1 WN=WN_FB WP=WP_FB LLN=3u LLP=3u}
|
||||
C {cmos_inv.sch} 570 -460 0 1 {name=X1 WN=WN_FB WP=WP_FB LLN=3u LLP=3u}
|
||||
C {iopin.sym} 250 -300 0 1 {name=p1 lab=A}
|
||||
C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"}
|
||||
C {capa.sym} 420 -500 1 0 {name=C1
|
||||
C {capa.sym} 550 -270 0 0 {name=C1
|
||||
m=1
|
||||
value=10f
|
||||
footprint=1206
|
||||
device="ceramic capacitor"}
|
||||
C {gnd.sym} 350 -500 0 0 {name=l2 lab=GND}
|
||||
C {gnd.sym} 550 -200 0 0 {name=l2 lab=0}
|
||||
C {lab_pin.sym} 550 -550 0 0 {name=l3 sig_type=std_logic lab=Y}
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
v {xschem version=2.9.9 file_version=1.2 }
|
||||
v {xschem version=3.1.0 file_version=1.2
|
||||
}
|
||||
G {}
|
||||
K {type=subcircuit
|
||||
function0="1 ~"
|
||||
|
|
@ -8,22 +9,40 @@ template="name=X1 WN=15u WP=45u LLN=3u LLP=3u m=1"
|
|||
V {}
|
||||
S {}
|
||||
E {}
|
||||
A 15 90 -350 14.14213562373095 135 360 {dash=2}
|
||||
P 2 5 60 -390 190 -390 190 -90 60 -90 60 -390 {dash=5}
|
||||
T {@name} 60 -405 0 0 0.2 0.2 {}
|
||||
A 15 90 -410 14.14213562373095 135 360 {dash=2}
|
||||
P 2 5 60 -450 270 -450 270 -90 60 -90 60 -450 {dash=5}
|
||||
T {@name} 60 -465 0 0 0.2 0.2 {}
|
||||
T {@symname} 63.75 -85 0 0 0.2 0.2 {}
|
||||
N 140 -260 140 -200 {lab=Z}
|
||||
N 100 -290 100 -170 {lab=A}
|
||||
N 60 -230 100 -230 {lab=A}
|
||||
N 140 -230 190 -230 {lab=Z}
|
||||
N 140 -340 140 -320 {lab=VDD}
|
||||
N 80 -350 80 -170 {lab=A}
|
||||
N 60 -230 80 -230 {lab=A}
|
||||
N 140 -400 140 -380 {lab=VDD}
|
||||
N 140 -140 140 -120 {lab=0}
|
||||
C {opin.sym} 190 -230 0 0 {name=p2 lab=Z}
|
||||
N 240 -230 270 -230 {
|
||||
lab=Z}
|
||||
N 140 -230 180 -230 {
|
||||
lab=D}
|
||||
N 140 -320 140 -290 {
|
||||
lab=#net1}
|
||||
N 140 -230 140 -200 {
|
||||
lab=D}
|
||||
N 80 -350 100 -350 {
|
||||
lab=A}
|
||||
N 80 -170 100 -170 {
|
||||
lab=A}
|
||||
C {opin.sym} 270 -230 0 0 {name=p2 lab=Z}
|
||||
C {ipin.sym} 60 -230 0 0 {name=p1 lab=A goto=0}
|
||||
C {vdd.sym} 140 -340 0 0 {name=l1 lab=VDD}
|
||||
C {vdd.sym} 140 -400 0 0 {name=l1 lab=VDD}
|
||||
C {lab_pin.sym} 140 -120 0 0 {name=l2 sig_type=std_logic lab=0}
|
||||
C {pmos4.sym} 120 -290 0 0 {name=M2 model=p w=WP l=LLP m=1 net_name=true}
|
||||
C {pmos4.sym} 120 -350 0 0 {name=M2 model=p w=WP l=LLP m=1 net_name=true}
|
||||
C {nmos4.sym} 120 -170 0 0 {name=M1 model=n w=WN l=LLN m=1 net_name=true}
|
||||
C {lab_pin.sym} 140 -170 0 1 {name=l3 sig_type=std_logic lab=0}
|
||||
C {lab_pin.sym} 140 -290 0 1 {name=l4 sig_type=std_logic lab=VDD}
|
||||
C {lab_pin.sym} 140 -350 0 1 {name=l4 sig_type=std_logic lab=VDD}
|
||||
C {title.sym} 160 -30 0 0 {name=l5 author="Stefan Schippers"}
|
||||
C {res.sym} 210 -230 1 0 {name=R1
|
||||
value=1k
|
||||
footprint=1206
|
||||
device=resistor
|
||||
m=1}
|
||||
C {lab_pin.sym} 140 -220 0 1 {name=l6 sig_type=std_logic lab=D}
|
||||
C {lab_pin.sym} 80 -320 0 1 {name=l7 sig_type=std_logic lab=A}
|
||||
C {ammeter.sym} 140 -260 0 0 {name=V1}
|
||||
|
|
|
|||
Loading…
Reference in New Issue