persists highlights on instances: remove highlighted instance from hash if user selects and presses ctrl-k as it is done for nets. Avoid instance highlight to also highlight net with identical name (example instance x1 and net x1). Verilog and Vhdl netlists handle duplicated (pass-through) pins
This commit is contained in:
Stefan Frederik
parent
137ca971d3
commit
3f627123b2
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@ -127,6 +127,20 @@ static Hilight_hashentry *hilight_hash_lookup(const char *token, int value, int
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}
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}
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/* wrapper function to hash highlighted instances, avoid clash with net names */
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Hilight_hashentry *inst_hilight_hash_lookup(const char *token, int value, int what)
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{
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char *inst_tok = NULL;
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size_t len = strlen(token) + 2; /* token plus one more character and \0 */
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Hilight_hashentry *entry;
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inst_tok = my_malloc(1568, len);
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/* instance name uglyfication: add a space at beginning so it will never match a valid net name */
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my_snprintf(inst_tok, len, " %s", token);
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entry = hilight_hash_lookup(inst_tok, value, what);
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my_free(1569, &inst_tok);
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return entry;
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}
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/* warning, in case of buses return only pointer to first found bus element */
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Hilight_hashentry *bus_hilight_hash_lookup(const char *token, int value, int what)
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{
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@ -637,6 +651,7 @@ int search(const char *tok, const char *val, int sub, int sel)
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dbg(1, "search(): setting hilight flag on inst %d\n",i);
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xctx->hilight_nets=1;
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xctx->inst[i].color = col;
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inst_hilight_hash_lookup(xctx->inst[i].instname, col, XINSERT_NOREPLACE);
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}
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}
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if(sel==1) {
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@ -786,6 +801,7 @@ static void drill_hilight(int mode)
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entry=bus_hilight_hash_lookup(netname, 0, XLOOKUP);
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if(entry && (hilight_connected_inst || (symbol->type && IS_LABEL_SH_OR_PIN(symbol->type))) ) {
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xctx->inst[i].color = entry->value;
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inst_hilight_hash_lookup(xctx->inst[i].instname, entry->value, XINSERT_NOREPLACE);
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}
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my_strdup(1225, &propagate_str, get_tok_value(rct[j].prop_ptr, "propag", 0));
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if(propagate_str) {
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@ -1167,31 +1183,42 @@ void propagate_hilights(int set, int clear, int mode)
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hilight_connected_inst = en_hi &&
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((xctx->inst[i].flags & HILIGHT_CONN) || ((xctx->inst[i].ptr+ xctx->sym)->flags & HILIGHT_CONN));
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/* hilight/clear instances with hilight=true attr set and en_hilight_conn_inst option is set ... */
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if(hilight_connected_inst && type && !IS_LABEL_SH_OR_PIN(type)) {
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int rects, j, nohilight_pins;
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if( (rects = (xctx->inst[i].ptr+ xctx->sym)->rects[PINLAYER]) > 0 ) {
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nohilight_pins = 1;
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for(j=0;j<rects;j++) {
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if( xctx->inst[i].node && xctx->inst[i].node[j]) {
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entry=bus_hilight_hash_lookup(xctx->inst[i].node[j], 0, XLOOKUP);
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if(entry) {
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if(set) {
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xctx->inst[i].color=entry->value;
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} else {
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nohilight_pins = 0; /* at least one connected net is hilighted: keep instance hilighted */
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if(type && !IS_LABEL_SH_OR_PIN(type)) {
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if (hilight_connected_inst) {
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int rects, j, nohilight_pins;
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if( (rects = (xctx->inst[i].ptr+ xctx->sym)->rects[PINLAYER]) > 0 ) {
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nohilight_pins = 1;
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for(j=0;j<rects;j++) {
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if( xctx->inst[i].node && xctx->inst[i].node[j]) {
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entry=bus_hilight_hash_lookup(xctx->inst[i].node[j], 0, XLOOKUP);
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if(entry) {
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if(set) {
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xctx->inst[i].color=entry->value;
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inst_hilight_hash_lookup(xctx->inst[i].instname, entry->value, XINSERT_NOREPLACE);
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} else {
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nohilight_pins = 0; /* at least one connected net is hilighted: keep instance hilighted */
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}
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break;
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}
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break;
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}
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}
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if(nohilight_pins && clear) {
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xctx->inst[i].color=-10000;
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}
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}
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if(nohilight_pins && clear) {
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xctx->inst[i].color=-10000;
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}
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}
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else {
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entry=inst_hilight_hash_lookup(xctx->inst[i].instname, 0, XLOOKUP);
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if (entry && set)
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xctx->inst[i].color=entry->value;
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}
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/* ... else hilight/clear pin/label instances attached to hilight nets */
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} else if(type && xctx->inst[i].node && IS_LABEL_SH_OR_PIN(type) ) {
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entry=bus_hilight_hash_lookup( xctx->inst[i].node[0], 0, XLOOKUP);
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if(entry && set) xctx->inst[i].color = entry->value;
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if(entry && set) {
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xctx->inst[i].color = entry->value;
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inst_hilight_hash_lookup(xctx->inst[i].instname, entry->value, XINSERT_NOREPLACE);
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}
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else if(!entry && clear) xctx->inst[i].color = -10000;
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}
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}
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@ -1668,6 +1695,7 @@ void hilight_net(int viewer)
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dbg(1, "hilight_net(): setting hilight flag on inst %d\n",n);
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xctx->hilight_nets=1;
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xctx->inst[n].color = xctx->hilight_color;
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inst_hilight_hash_lookup(xctx->inst[n].instname, xctx->hilight_color, XINSERT_NOREPLACE);
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if(type && (!strcmp(type, "current_probe") || !strcmp(type, "vsource")) ) {
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if(viewer == XSCHEM_GRAPH) send_current_to_graph(&s, sim_is_xyce, xctx->inst[n].instname);
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else if(viewer == GAW) send_current_to_gaw(sim_is_xyce, xctx->inst[n].instname);
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@ -1708,8 +1736,12 @@ void unhilight_net(void)
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break;
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case ELEMENT:
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type = (xctx->inst[n].ptr+ xctx->sym)->type;
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if( type && xctx->inst[n].node && IS_LABEL_SH_OR_PIN(type) ) { /* instance must have a pin! */
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bus_hilight_hash_lookup(xctx->inst[n].node[0], xctx->hilight_color, XDELETE);
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if( type) {
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if( xctx->inst[n].node && IS_LABEL_SH_OR_PIN(type) ) { /* instance must have a pin! */
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bus_hilight_hash_lookup(xctx->inst[n].node[0], xctx->hilight_color, XDELETE);
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} else {
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inst_hilight_hash_lookup(xctx->inst[n].instname, xctx->hilight_color, XDELETE);
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}
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}
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xctx->inst[n].color = -10000;
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break;
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76
src/token.c
76
src/token.c
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@ -890,14 +890,23 @@ static void print_vhdl_primitive(FILE *fd, int inst) /* netlist primitives, 200
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else if(strcmp(token,"@pinlist")==0) /* of course pinlist must not be present */
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/* in hash table. print multiplicity */
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{ /* and node number: m1 n1 m2 n2 .... */
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Int_hashtable table = {NULL, 0};
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int first = 1;
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int_hash_init(&table, 37);
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for(i=0;i<no_of_pins;i++)
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{
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char *prop = (xctx->inst[inst].ptr + xctx->sym)->rect[PINLAYER][i].prop_ptr;
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if(strcmp(get_tok_value(prop,"vhdl_ignore",0), "true")) {
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str_ptr = net_name(inst,i, &multip, 0, 1);
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fprintf(fd, "----pin(%s) ", str_ptr);
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const char *name = get_tok_value(prop,"name",0);
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if(!int_hash_lookup(&table, name, 1, XINSERT_NOREPLACE)) {
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if(!first) fprintf(fd, " , ");
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str_ptr = net_name(inst,i, &multip, 0, 1);
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fprintf(fd, "----pin(%s) ", str_ptr);
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first = 0;
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}
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}
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}
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int_hash_free(&table);
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}
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else if(token[0]=='@' && token[1]=='@') { /* recognize single pins 15112003 */
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for(i=0;i<no_of_pins;i++) {
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@ -1204,6 +1213,7 @@ void print_vhdl_element(FILE *fd, int inst)
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int escape=0;
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xRect *pinptr;
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const char *fmt_attr = NULL;
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Int_hashtable table = {NULL, 0};
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fmt_attr = xctx->format ? xctx->format : "vhdl_format";
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if(get_tok_value((xctx->inst[inst].ptr + xctx->sym)->prop_ptr, fmt_attr, 2)[0] != '\0') {
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@ -1322,19 +1332,24 @@ void print_vhdl_element(FILE *fd, int inst)
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fprintf(fd, "port map(\n" );
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tmp=0;
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pinptr = (xctx->inst[inst].ptr + xctx->sym)->rect[PINLAYER];
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int_hash_init(&table, 37);
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for(i=0;i<no_of_pins;i++)
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{
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if(strcmp(get_tok_value(pinptr[i].prop_ptr,"vhdl_ignore",0), "true")) {
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if( (str_ptr = net_name(inst,i, &multip, 0, 1)) )
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{
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if(tmp) fprintf(fd, " ,\n");
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fprintf(fd, " %s => %s",
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get_tok_value((xctx->inst[inst].ptr + xctx->sym)->rect[PINLAYER][i].prop_ptr,"name",0),
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str_ptr);
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tmp=1;
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const char *name = get_tok_value(pinptr[i].prop_ptr, "name", 0);
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if(!int_hash_lookup(&table, name, 1, XINSERT_NOREPLACE)) {
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if( (str_ptr = net_name(inst,i, &multip, 0, 1)) )
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{
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if(tmp) fprintf(fd, " ,\n");
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fprintf(fd, " %s => %s",
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get_tok_value((xctx->inst[inst].ptr + xctx->sym)->rect[PINLAYER][i].prop_ptr,"name",0),
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str_ptr);
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tmp=1;
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}
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}
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}
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}
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int_hash_free(&table);
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fprintf(fd, "\n);\n\n");
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dbg(2, "print_vhdl_element(): ------- end ------ \n");
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my_free(992, &name);
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@ -2218,8 +2233,8 @@ void print_tedax_element(FILE *fd, int inst)
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topsch = get_trailing_path(xctx->sch[0], 0, 1);
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fputs(topsch, fd);
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}
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else if(strcmp(token,"@pinlist")==0) /* of course pinlist must not be present */
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/* in hash table. print multiplicity */
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else if(strcmp(token,"@pinlist")==0)
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/* print multiplicity */
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{ /* and node number: m1 n1 m2 n2 .... */
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for(i=0;i<no_of_pins;i++)
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{
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@ -2338,6 +2353,7 @@ static void print_verilog_primitive(FILE *fd, int inst) /* netlist switch level
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size_t token_pos=0;
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int escape=0;
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int no_of_pins=0;
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int symbol = xctx->inst[inst].ptr;
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/* Inst_hashentry *ptr; */
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const char *fmt_attr = NULL;
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@ -2449,12 +2465,21 @@ static void print_verilog_primitive(FILE *fd, int inst) /* netlist switch level
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else if(strcmp(token,"@pinlist")==0) /* of course pinlist must not be present */
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/* in hash table. print multiplicity */
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{ /* and node number: m1 n1 m2 n2 .... */
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for(i=0;i<no_of_pins;i++)
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{
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str_ptr = net_name(inst,i, &multip, 0, 1);
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fprintf(fd, "----pin(%s) ", str_ptr);
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if(i < no_of_pins - 1) fprintf(fd, " , ");
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Int_hashtable table = {NULL, 0};
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int first = 1;
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int_hash_init(&table, 37);
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for(i=0;i<no_of_pins;i++) {
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if(strcmp(get_tok_value(xctx->sym[symbol].rect[PINLAYER][i].prop_ptr,"verilog_ignore",0), "true")) {
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const char *name = get_tok_value(xctx->sym[symbol].rect[PINLAYER][i].prop_ptr,"name",0);
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if(!int_hash_lookup(&table, name, 1, XINSERT_NOREPLACE)) {
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if(!first) fprintf(fd, " , ");
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str_ptr = net_name(inst,i, &multip, 0, 1);
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fprintf(fd, "----pin(%s) ", str_ptr);
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first = 0;
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}
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}
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}
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int_hash_free(&table);
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}
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else if(token[0]=='@' && token[1]=='@') { /* recognize single pins 15112003 */
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for(i=0;i<no_of_pins;i++) {
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@ -2534,6 +2559,7 @@ void print_verilog_element(FILE *fd, int inst)
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size_t token_pos=0, value_pos=0;
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int quote=0;
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const char *fmt_attr = NULL;
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Int_hashtable table = {NULL, 0};
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fmt_attr = xctx->format ? xctx->format : "verilog_format";
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if(get_tok_value((xctx->inst[inst].ptr + xctx->sym)->prop_ptr, fmt_attr, 2)[0] != '\0') {
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@ -2635,21 +2661,23 @@ void print_verilog_element(FILE *fd, int inst)
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dbg(2, "print_verilog_element(): printing port maps \n");
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/* print port map */
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tmp=0;
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int_hash_init(&table, 37);
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for(i=0;i<no_of_pins;i++)
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{
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xSymbol *ptr = xctx->inst[inst].ptr + xctx->sym;
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if(strcmp(get_tok_value(ptr->rect[PINLAYER][i].prop_ptr,"verilog_ignore",0), "true")) {
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if( (str_ptr = net_name(inst,i, &multip, 0, 1)) )
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{
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if(tmp) fprintf(fd,"\n");
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fprintf(fd, " ?%d %s %s ", multip,
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get_tok_value(ptr->rect[PINLAYER][i].prop_ptr,"name",0),
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str_ptr);
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tmp=1;
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const char *name = get_tok_value(ptr->rect[PINLAYER][i].prop_ptr, "name", 0);
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if(!int_hash_lookup(&table, name, 1, XINSERT_NOREPLACE)) {
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if( (str_ptr = net_name(inst,i, &multip, 0, 1)) )
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{
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if(tmp) fprintf(fd,"\n");
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fprintf(fd, " ?%d %s %s ", multip, get_tok_value(ptr->rect[PINLAYER][i].prop_ptr,"name",0), str_ptr);
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tmp=1;
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}
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}
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}
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}
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int_hash_free(&table);
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if(v_extra) {
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const char *val;
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for(extra_ptr = v_extra; ; extra_ptr=NULL) {
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@ -59,9 +59,9 @@ BEGIN{
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/^---- end primitive/{
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primitive=0
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$0 = primitive_line
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split(primitive_line, primitive_line_sep, /[^ \n\t]+/)
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gsub(/----pin\(/, " ----pin(",$0)
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gsub(/----name\(/, " ----name(",$0)
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split($0, primitive_line_sep, /[^ \n\t]+/)
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for(j=1;j<= primitive_mult; j++) {
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prefix=""
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# print $0 > "/dev/stderr"
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@ -108,7 +108,9 @@ BEGIN{
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sub(/\]/,"", prim_field_array[j])
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printf "%s%s", prefix prim_field_array[j], primitive_line_sep[i+1]
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}
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else printf "%s%s", prim_field, primitive_line_sep[i+1]
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else {
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printf "%s%s", prim_field, primitive_line_sep[i+1]
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}
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prefix=""
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} # end for i
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printf "\n"
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@ -449,6 +449,8 @@ void verilog_block_netlist(FILE *fd, int i)
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if(sym_def[0]) {
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fprintf(fd, "%s\n", sym_def);
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} else {
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Int_hashtable table = {NULL, 0};
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int_hash_init(&table, 37);
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my_strdup(1040, &extra, get_tok_value(xctx->sym[i].prop_ptr, "verilog_extra", 0));
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my_strdup(1563, &extra2, get_tok_value(xctx->sym[i].prop_ptr, "verilog_extra", 0));
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fprintf(fd, "// sch_path: %s\n", filename);
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@ -481,12 +483,16 @@ void verilog_block_netlist(FILE *fd, int i)
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for(j=0;j<xctx->sym[i].rects[PINLAYER];j++)
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{
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if(strcmp(get_tok_value(xctx->sym[i].rect[PINLAYER][j].prop_ptr,"verilog_ignore",0), "true")) {
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str_tmp = get_tok_value(xctx->sym[i].rect[PINLAYER][j].prop_ptr,"name",0);
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if(tmp) fprintf(fd, " ,\n");
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tmp++;
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fprintf(fd," %s", str_tmp ? str_tmp : "<NULL>");
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const char *name = get_tok_value(xctx->sym[i].rect[PINLAYER][j].prop_ptr, "name", 0);
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if(!int_hash_lookup(&table, name, 1, XINSERT_NOREPLACE)) {
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dbg(0, "verilog port: %s\n", name);
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if(tmp) fprintf(fd, " ,\n");
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tmp++;
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fprintf(fd," %s", name);
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}
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}
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}
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int_hash_free(&table);
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if(extra) {
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for(extra_ptr = extra; ; extra_ptr=NULL) {
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@ -503,6 +509,7 @@ void verilog_block_netlist(FILE *fd, int i)
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/* print module default parameters */
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print_verilog_param(fd,i);
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/* print port types */
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int_hash_init(&table, 37);
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for(j=0;j<xctx->sym[i].rects[PINLAYER];j++)
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{
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if(strcmp(get_tok_value(xctx->sym[i].rect[PINLAYER][j].prop_ptr,"verilog_ignore",0), "true")) {
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@ -517,17 +524,17 @@ void verilog_block_netlist(FILE *fd, int i)
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if(!sig_type || sig_type[0]=='\0') my_strdup(568, &sig_type,"wire");
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}
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str_tmp = get_tok_value(xctx->sym[i].rect[PINLAYER][j].prop_ptr,"name",0);
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fprintf(fd," %s %s ;\n",
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strcmp(dir_tmp,"in")? ( strcmp(dir_tmp,"out")? "inout" :"output" ) : "input",
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str_tmp ? str_tmp : "<NULL>");
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fprintf(fd," %s %s",
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sig_type,
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str_tmp ? str_tmp : "<NULL>");
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if(port_value &&port_value[0])
|
||||
fprintf(fd," = %s", port_value);
|
||||
fprintf(fd," ;\n");
|
||||
if(!int_hash_lookup(&table, str_tmp, 1, XINSERT_NOREPLACE)) {
|
||||
fprintf(fd," %s %s ;\n",
|
||||
strcmp(dir_tmp,"in")? ( strcmp(dir_tmp,"out")? "inout" :"output" ) : "input", str_tmp);
|
||||
fprintf(fd," %s %s", sig_type, str_tmp);
|
||||
if(port_value &&port_value[0])
|
||||
fprintf(fd," = %s", port_value);
|
||||
fprintf(fd," ;\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
int_hash_free(&table);
|
||||
if(extra2) {
|
||||
saveptr1 = NULL;
|
||||
for(extra_ptr = extra2; ; extra_ptr=NULL) {
|
||||
|
|
|
|||
|
|
@ -349,12 +349,14 @@ void global_vhdl_netlist(int global) /* netlister driver */
|
|||
/* xctx->sym can be SCH or SYM, use hash to avoid writing duplicate subckt */
|
||||
my_strdup(317, &subckt_name, get_cell(xctx->sym[j].name, 0));
|
||||
if (str_hash_lookup(&subckt_table, subckt_name, "", XLOOKUP)==NULL) {
|
||||
Int_hashtable table = {NULL, 0};
|
||||
str_hash_lookup(&subckt_table, subckt_name, "", XINSERT);
|
||||
/* component generics */
|
||||
print_generic(fd,"component", j);
|
||||
|
||||
/* component ports */
|
||||
tmp=0;
|
||||
int_hash_init(&table, 37);
|
||||
for(i=0;i<xctx->sym[j].rects[PINLAYER];i++)
|
||||
{
|
||||
if(strcmp(get_tok_value(xctx->sym[j].rect[PINLAYER][i].prop_ptr,"vhdl_ignore",0), "true")) {
|
||||
|
|
@ -365,16 +367,18 @@ void global_vhdl_netlist(int global) /* netlister driver */
|
|||
if(!sig_type || sig_type[0]=='\0') my_strdup(589, &sig_type,"std_logic");
|
||||
my_strdup(590, &dir_tmp, get_tok_value(xctx->sym[j].rect[PINLAYER][i].prop_ptr,"dir",0) );
|
||||
str_tmp = get_tok_value(xctx->sym[j].rect[PINLAYER][i].prop_ptr,"name",0);
|
||||
if(!tmp) fprintf(fd, "port (\n");
|
||||
if(tmp) fprintf(fd, " ;\n");
|
||||
fprintf(fd," %s : %s %s",str_tmp ? str_tmp : "<NULL>",
|
||||
dir_tmp ? dir_tmp : "<NULL>", sig_type);
|
||||
my_free(1085, &dir_tmp);
|
||||
if(port_value &&port_value[0])
|
||||
fprintf(fd," := %s", port_value);
|
||||
tmp=1;
|
||||
if(!int_hash_lookup(&table, str_tmp, 1, XINSERT_NOREPLACE)) {
|
||||
if(!tmp) fprintf(fd, "port (\n");
|
||||
if(tmp) fprintf(fd, " ;\n");
|
||||
fprintf(fd," %s : %s %s",str_tmp, dir_tmp ? dir_tmp : "<NULL>", sig_type);
|
||||
my_free(1085, &dir_tmp);
|
||||
if(port_value &&port_value[0])
|
||||
fprintf(fd," := %s", port_value);
|
||||
tmp=1;
|
||||
}
|
||||
}
|
||||
}
|
||||
int_hash_free(&table);
|
||||
if(tmp) fprintf(fd, "\n);\n");
|
||||
fprintf(fd, "end component ;\n\n");
|
||||
}
|
||||
|
|
@ -540,6 +544,7 @@ void vhdl_block_netlist(FILE *fd, int i)
|
|||
if(sym_def[0]) {
|
||||
fprintf(fd, "%s\n", sym_def);
|
||||
} else {
|
||||
Int_hashtable table = {NULL, 0};
|
||||
fprintf(fd, "-- sch_path: %s\n", filename);
|
||||
load_schematic(1,filename, 0);
|
||||
dbg(1, "vhdl_block_netlist(): packages\n");
|
||||
|
|
@ -575,6 +580,7 @@ void vhdl_block_netlist(FILE *fd, int i)
|
|||
dbg(1, "vhdl_block_netlist(): entity ports\n");
|
||||
/* print entity ports */
|
||||
tmp=0;
|
||||
int_hash_init(&table, 37);
|
||||
for(j=0;j<xctx->sym[i].rects[PINLAYER];j++)
|
||||
{
|
||||
if(strcmp(get_tok_value(xctx->sym[i].rect[PINLAYER][j].prop_ptr,"vhdl_ignore",0), "true")) {
|
||||
|
|
@ -585,16 +591,19 @@ void vhdl_block_netlist(FILE *fd, int i)
|
|||
if(!sig_type || sig_type[0]=='\0') my_strdup(594, &sig_type,"std_logic");
|
||||
my_strdup(595, &dir_tmp, get_tok_value(xctx->sym[i].rect[PINLAYER][j].prop_ptr,"dir",0) );
|
||||
str_tmp = get_tok_value(xctx->sym[i].rect[PINLAYER][j].prop_ptr,"name",0);
|
||||
if(tmp) fprintf(fd, " ;\n");
|
||||
if(!tmp) fprintf(fd,"port (\n");
|
||||
fprintf(fd," %s : %s %s",str_tmp ? str_tmp : "<NULL>",
|
||||
dir_tmp ? dir_tmp : "<NULL>", sig_type);
|
||||
my_free(1092, &dir_tmp);
|
||||
if(port_value &&port_value[0])
|
||||
fprintf(fd," := %s", port_value);
|
||||
tmp=1;
|
||||
if(!int_hash_lookup(&table, str_tmp, 1, XINSERT_NOREPLACE)) {
|
||||
if(tmp) fprintf(fd, " ;\n");
|
||||
if(!tmp) fprintf(fd,"port (\n");
|
||||
fprintf(fd," %s : %s %s",str_tmp ? str_tmp : "<NULL>",
|
||||
dir_tmp ? dir_tmp : "<NULL>", sig_type);
|
||||
my_free(1092, &dir_tmp);
|
||||
if(port_value &&port_value[0])
|
||||
fprintf(fd," := %s", port_value);
|
||||
tmp=1;
|
||||
}
|
||||
}
|
||||
}
|
||||
int_hash_free(&table);
|
||||
if(tmp) fprintf(fd, "\n);\n");
|
||||
|
||||
dbg(1, "vhdl_block_netlist(): port attributes\n");
|
||||
|
|
@ -650,9 +659,9 @@ void vhdl_block_netlist(FILE *fd, int i)
|
|||
if(!found) continue;
|
||||
/* component generics */
|
||||
print_generic(fd, "component",j);
|
||||
|
||||
/* component ports */
|
||||
tmp=0;
|
||||
int_hash_init(&table, 37);
|
||||
for(k=0;k<xctx->sym[j].rects[PINLAYER];k++)
|
||||
{
|
||||
if(strcmp(get_tok_value(xctx->sym[j].rect[PINLAYER][k].prop_ptr,"vhdl_ignore",0), "true")) {
|
||||
|
|
@ -664,16 +673,17 @@ void vhdl_block_netlist(FILE *fd, int i)
|
|||
if(!sig_type || sig_type[0]=='\0') my_strdup(599, &sig_type,"std_logic");
|
||||
my_strdup(600, &dir_tmp, get_tok_value(xctx->sym[j].rect[PINLAYER][k].prop_ptr,"dir",0) );
|
||||
str_tmp = get_tok_value(xctx->sym[j].rect[PINLAYER][k].prop_ptr,"name",0);
|
||||
if(!tmp) fprintf(fd, "port (\n");
|
||||
if(tmp) fprintf(fd, " ;\n");
|
||||
fprintf(fd," %s : %s %s",str_tmp ? str_tmp : "<NULL>",
|
||||
dir_tmp ? dir_tmp : "<NULL>", sig_type);
|
||||
my_free(1093, &dir_tmp);
|
||||
if(port_value &&port_value[0])
|
||||
fprintf(fd," := %s", port_value);
|
||||
tmp=1;
|
||||
if(!int_hash_lookup(&table, str_tmp, 1, XINSERT_NOREPLACE)) {
|
||||
if(!tmp) fprintf(fd, "port (\n");
|
||||
if(tmp) fprintf(fd, " ;\n");
|
||||
fprintf(fd," %s : %s %s",str_tmp, dir_tmp ? dir_tmp : "<NULL>", sig_type);
|
||||
my_free(1093, &dir_tmp);
|
||||
if(port_value &&port_value[0]) fprintf(fd," := %s", port_value);
|
||||
tmp=1;
|
||||
}
|
||||
}
|
||||
}
|
||||
int_hash_free(&table);
|
||||
if(tmp) fprintf(fd, "\n);\n");
|
||||
fprintf(fd, "end component ;\n\n");
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1099,6 +1099,8 @@ extern const char *get_file_path(char *f);
|
|||
extern int save(int confirm);
|
||||
extern void save_ascii_string(const char *ptr, FILE *fd, int newline);
|
||||
extern Hilight_hashentry *bus_hilight_hash_lookup(const char *token, int value, int what) ;
|
||||
/* wrapper function to hash highlighted instances, avoid clash with net names */
|
||||
extern Hilight_hashentry *inst_hilight_hash_lookup(const char *token, int value, int what);
|
||||
extern Hilight_hashentry *hilight_lookup(const char *token, int value, int what);
|
||||
extern int search(const char *tok, const char *val, int sub, int sel);
|
||||
extern int process_options(int argc, char **argv);
|
||||
|
|
|
|||
|
|
@ -191,14 +191,14 @@ proc netlist_test {} {
|
|||
global netlist_dir
|
||||
foreach {f t h} {
|
||||
rom8k.sch spice 1975420796
|
||||
greycnt.sch verilog 3991013786
|
||||
greycnt.sch verilog 2415454714
|
||||
autozero_comp.sch spice 2275498269
|
||||
loading.sch vhdl 584526899
|
||||
mos_power_ampli.sch spice 1004049459
|
||||
hierarchical_tedax.sch tedax 998070173
|
||||
LCC_instances.sch spice 2610855064
|
||||
pcb_test1.sch tedax 1925087189
|
||||
test_doublepin.sch spice 2249536600
|
||||
test_doublepin.sch spice 1447757360
|
||||
simulate_ff.sch spice 1321596936
|
||||
} {
|
||||
xschem set netlist_type $t
|
||||
|
|
|
|||
|
|
@ -2,22 +2,7 @@ v {xschem version=3.1.0 file_version=1.2
|
|||
}
|
||||
G {}
|
||||
K {}
|
||||
V {
|
||||
|
||||
initial begin
|
||||
$dumpfile("dumpfile.vcd");
|
||||
$dumpvars;
|
||||
A=0;
|
||||
end
|
||||
|
||||
integer i = 0;
|
||||
always begin
|
||||
i = i + 1;
|
||||
#100000;
|
||||
$display("time= %t: A= %08b Y= %08b", $time, A, Y);
|
||||
A=~A;
|
||||
if(i==20) $finish;
|
||||
end}
|
||||
V {}
|
||||
S {}
|
||||
E {}
|
||||
C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"}
|
||||
|
|
|
|||
|
|
@ -3,21 +3,7 @@ v {xschem version=3.1.0 file_version=1.2
|
|||
G {}
|
||||
K {}
|
||||
V {
|
||||
|
||||
initial begin
|
||||
$dumpfile("dumpfile.vcd");
|
||||
$dumpvars;
|
||||
A=0;
|
||||
end
|
||||
|
||||
integer i = 0;
|
||||
always begin
|
||||
i = i + 1;
|
||||
#100000;
|
||||
$display("time= %t: A= %08b Y= %08b", $time, A, Y);
|
||||
A=~A;
|
||||
if(i==20) $finish;
|
||||
end}
|
||||
}
|
||||
S {va a 0 pwl 0 0 100n 0 101n 3
|
||||
vvcc vcc 0 dc 3
|
||||
vvss vss 0 dc 0
|
||||
|
|
@ -35,17 +21,17 @@ lab=AA[3:0]}
|
|||
N 480 -870 630 -870 {
|
||||
lab=BB}
|
||||
N 480 -830 510 -830 {
|
||||
lab=ZZ5}
|
||||
lab=ZZ[5]}
|
||||
N 930 -830 960 -830 {
|
||||
lab=ZZ6}
|
||||
lab=ZZ[6]}
|
||||
N 480 -1060 510 -1060 {
|
||||
lab=ZZ3}
|
||||
lab=ZZ[3]}
|
||||
N 930 -1060 960 -1060 {
|
||||
lab=ZZ4}
|
||||
lab=ZZ[4]}
|
||||
N 480 -1290 510 -1290 {
|
||||
lab=ZZ1}
|
||||
lab=ZZ[1]}
|
||||
N 930 -1290 960 -1290 {
|
||||
lab=ZZ2}
|
||||
lab=ZZ[2]}
|
||||
N 480 -1390 630 -1390 {
|
||||
lab=RRSSTT}
|
||||
N 480 -1370 630 -1370 {
|
||||
|
|
@ -63,9 +49,9 @@ lab=AA[3:0]}
|
|||
N 480 -660 660 -660 {
|
||||
lab=BB}
|
||||
N 480 -620 510 -620 {
|
||||
lab=ZZ7}
|
||||
lab=ZZ[7]}
|
||||
N 630 -620 660 -620 {
|
||||
lab=ZZ8}
|
||||
lab=ZZ[8]}
|
||||
N 960 -720 1080 -720 {
|
||||
lab=RRSSTT}
|
||||
N 960 -700 1080 -700 {
|
||||
|
|
@ -75,23 +61,23 @@ lab=AA[3:0]}
|
|||
N 960 -660 1080 -660 {
|
||||
lab=BB}
|
||||
N 1380 -620 1410 -620 {
|
||||
lab=ZZ9}
|
||||
N 480 -510 660 -510 {
|
||||
lab=ZZ[9]}
|
||||
N 410 -510 660 -510 {
|
||||
lab=#net1}
|
||||
N 480 -490 660 -490 {
|
||||
N 410 -490 660 -490 {
|
||||
lab=#net2}
|
||||
N 480 -470 660 -470 {
|
||||
N 410 -470 660 -470 {
|
||||
lab=#net3}
|
||||
N 480 -450 660 -450 {
|
||||
N 410 -450 660 -450 {
|
||||
lab=#net4}
|
||||
N 480 -410 510 -410 {
|
||||
lab=ZZ12}
|
||||
N 410 -410 440 -410 {
|
||||
lab=ZZ[12]}
|
||||
N 630 -410 660 -410 {
|
||||
lab=ZZ11}
|
||||
lab=ZZ[11]}
|
||||
N 1260 -410 1290 -410 {
|
||||
lab=ZZ10}
|
||||
lab=ZZ[10]}
|
||||
N 1520 -990 1550 -990 {
|
||||
lab=ZZ13}
|
||||
lab=ZZ[13]}
|
||||
N 1170 -1090 1220 -1090 {
|
||||
lab=RRSSTT}
|
||||
N 1170 -1070 1220 -1070 {
|
||||
|
|
@ -101,7 +87,7 @@ lab=AA[3:0]}
|
|||
N 1170 -1030 1220 -1030 {
|
||||
lab=BB}
|
||||
N 1190 -1250 1220 -1250 {
|
||||
lab=ZZ14}
|
||||
lab=ZZ[14]}
|
||||
N 1170 -1350 1220 -1350 {
|
||||
lab=RRSSTT}
|
||||
N 1170 -1330 1220 -1330 {
|
||||
|
|
@ -110,33 +96,33 @@ N 1170 -1310 1220 -1310 {
|
|||
lab=AA[3:0]}
|
||||
N 1170 -1290 1220 -1290 {
|
||||
lab=BB}
|
||||
N 620 -280 660 -280 {
|
||||
N 670 -280 710 -280 {
|
||||
lab=#net5}
|
||||
N 480 -260 660 -260 {
|
||||
N 480 -260 710 -260 {
|
||||
lab=#net6}
|
||||
N 480 -240 660 -240 {
|
||||
N 480 -240 710 -240 {
|
||||
lab=#net7}
|
||||
N 480 -220 660 -220 {
|
||||
N 480 -220 710 -220 {
|
||||
lab=#net8}
|
||||
N 480 -180 510 -180 {
|
||||
lab=ZZ17}
|
||||
N 630 -180 660 -180 {
|
||||
lab=ZZ16}
|
||||
N 960 -280 1080 -280 {
|
||||
lab=ZZ[17]}
|
||||
N 680 -180 710 -180 {
|
||||
lab=ZZ[16]}
|
||||
N 1010 -280 1080 -280 {
|
||||
lab=#net5}
|
||||
N 960 -260 1080 -260 {
|
||||
N 1010 -260 1080 -260 {
|
||||
lab=#net6}
|
||||
N 960 -240 1080 -240 {
|
||||
N 1010 -240 1080 -240 {
|
||||
lab=#net7}
|
||||
N 960 -220 1080 -220 {
|
||||
N 1010 -220 1080 -220 {
|
||||
lab=#net8}
|
||||
N 1380 -180 1410 -180 {
|
||||
lab=ZZ15}
|
||||
lab=ZZ[15]}
|
||||
N 10 -260 40 -260 {
|
||||
lab=#net9}
|
||||
N 120 -260 180 -260 {
|
||||
lab=#net6}
|
||||
N 70 -450 100 -450 {
|
||||
N 0 -450 30 -450 {
|
||||
lab=#net10}
|
||||
N 1260 -510 1440 -510 {
|
||||
lab=#net1}
|
||||
|
|
@ -147,18 +133,18 @@ lab=#net3}
|
|||
N 1260 -450 1440 -450 {
|
||||
lab=#net4}
|
||||
N 1740 -310 1770 -310 {
|
||||
lab=ZZ18}
|
||||
lab=ZZ[18]}
|
||||
N 1740 -410 1740 -310 {
|
||||
lab=ZZ18}
|
||||
lab=ZZ[18]}
|
||||
N 2040 -310 2070 -310 {
|
||||
lab=ZZ19}
|
||||
lab=ZZ[19]}
|
||||
N 2040 -410 2040 -310 {
|
||||
lab=ZZ19}
|
||||
N 620 -350 620 -280 {
|
||||
lab=ZZ[19]}
|
||||
N 670 -350 670 -280 {
|
||||
lab=#net5}
|
||||
N 620 -350 680 -350 {
|
||||
N 670 -350 730 -350 {
|
||||
lab=#net5}
|
||||
N 760 -350 810 -350 {
|
||||
N 810 -350 860 -350 {
|
||||
lab=#net11}
|
||||
N 1110 -920 1260 -920 {
|
||||
lab=RRSSTT}
|
||||
|
|
@ -169,7 +155,7 @@ lab=AA[3:0]}
|
|||
N 1110 -860 1260 -860 {
|
||||
lab=BB}
|
||||
N 1560 -820 1590 -820 {
|
||||
lab=ZZ20}
|
||||
lab=ZZ[20]}
|
||||
N 1690 -920 1760 -920 {
|
||||
lab=RRSSTT}
|
||||
N 1560 -900 1760 -900 {
|
||||
|
|
@ -179,7 +165,7 @@ lab=AA[3:0]}
|
|||
N 1730 -860 1760 -860 {
|
||||
lab=BB}
|
||||
N 1730 -820 1760 -820 {
|
||||
lab=ZZ21}
|
||||
lab=ZZ[21]}
|
||||
N 2060 -880 2080 -880 {
|
||||
lab=AA[3:0]}
|
||||
N 2060 -860 2080 -860 {
|
||||
|
|
@ -211,7 +197,7 @@ lab=BB}
|
|||
N 1690 -1070 1780 -1070 {
|
||||
lab=RRSSTT}
|
||||
N 2330 -930 2360 -930 {
|
||||
lab=ZZ22}
|
||||
lab=ZZ[22]}
|
||||
N 2660 -990 2690 -990 {
|
||||
lab=#net12}
|
||||
N 2660 -970 2690 -970 {
|
||||
|
|
@ -224,7 +210,7 @@ N 2300 -970 2300 -950 {
|
|||
lab=RRSSTT}
|
||||
N 2300 -970 2360 -970 {
|
||||
lab=RRSSTT}
|
||||
N 480 -280 620 -280 {
|
||||
N 480 -280 670 -280 {
|
||||
lab=#net5}
|
||||
N 1560 -920 1690 -920 {
|
||||
lab=RRSSTT}
|
||||
|
|
@ -259,8 +245,8 @@ net_name=true}
|
|||
C {doublepin.sym} 780 -880 0 0 {name=x2
|
||||
net_name=true}
|
||||
C {lab_wire.sym} 550 -890 0 0 {name=l2 sig_type=std_logic lab=AA[3:0]}
|
||||
C {lab_pin.sym} 510 -830 0 1 {name=p3 lab=ZZ5}
|
||||
C {lab_pin.sym} 960 -830 0 1 {name=p5 lab=ZZ6}
|
||||
C {lab_pin.sym} 510 -830 0 1 {name=p3 lab=ZZ[5]}
|
||||
C {lab_pin.sym} 960 -830 0 1 {name=p5 lab=ZZ[6]}
|
||||
C {lab_wire.sym} 550 -930 0 0 {name=l3 sig_type=std_logic lab=RRSSTT}
|
||||
C {lab_wire.sym} 550 -910 0 0 {name=l4 sig_type=std_logic lab=CCKK}
|
||||
C {lab_wire.sym} 550 -870 0 0 {name=l5 sig_type=std_logic lab=BB}
|
||||
|
|
@ -269,8 +255,8 @@ net_name=true}
|
|||
C {doublepin.sym} 780 -1110 0 0 {name=x4
|
||||
net_name=true}
|
||||
C {lab_pin.sym} 180 -1120 0 0 {name=l6 sig_type=std_logic lab=AA[3:0]}
|
||||
C {lab_pin.sym} 510 -1060 0 1 {name=p1 lab=ZZ3}
|
||||
C {lab_pin.sym} 960 -1060 0 1 {name=p2 lab=ZZ4}
|
||||
C {lab_pin.sym} 510 -1060 0 1 {name=p1 lab=ZZ[3]}
|
||||
C {lab_pin.sym} 960 -1060 0 1 {name=p2 lab=ZZ[4]}
|
||||
C {lab_pin.sym} 180 -1160 0 0 {name=l7 sig_type=std_logic lab=RRSSTT}
|
||||
C {lab_pin.sym} 180 -1140 0 0 {name=l8 sig_type=std_logic lab=CCKK}
|
||||
C {lab_pin.sym} 180 -1100 0 0 {name=l9 sig_type=std_logic lab=BB}
|
||||
|
|
@ -283,8 +269,8 @@ net_name=true}
|
|||
C {doublepin.sym} 780 -1340 0 0 {name=x6
|
||||
net_name=true}
|
||||
C {lab_pin.sym} 180 -1350 0 0 {name=l14 sig_type=std_logic lab=AA[3:0]}
|
||||
C {lab_pin.sym} 510 -1290 0 1 {name=p4 lab=ZZ1}
|
||||
C {lab_pin.sym} 960 -1290 0 1 {name=p6 lab=ZZ2}
|
||||
C {lab_pin.sym} 510 -1290 0 1 {name=p4 lab=ZZ[1]}
|
||||
C {lab_pin.sym} 960 -1290 0 1 {name=p6 lab=ZZ[2]}
|
||||
C {lab_pin.sym} 180 -1390 0 0 {name=l15 sig_type=std_logic lab=RRSSTT}
|
||||
C {lab_pin.sym} 180 -1370 0 0 {name=l16 sig_type=std_logic lab=CCKK}
|
||||
C {lab_pin.sym} 180 -1330 0 0 {name=l17 sig_type=std_logic lab=BB}
|
||||
|
|
@ -299,8 +285,8 @@ C {lab_wire.sym} 550 -1330 0 0 {name=l25 sig_type=std_logic lab=BB}
|
|||
C {lab_pin.sym} 180 -660 0 0 {name=l33 sig_type=std_logic lab=BB}
|
||||
C {doublepin.sym} 330 -880 0 0 {name=x1
|
||||
net_name=true}
|
||||
C {lab_pin.sym} 510 -620 0 1 {name=p7 lab=ZZ7}
|
||||
C {lab_pin.sym} 630 -620 0 0 {name=p8 lab=ZZ8}
|
||||
C {lab_pin.sym} 510 -620 0 1 {name=p7 lab=ZZ[7]}
|
||||
C {lab_pin.sym} 630 -620 0 0 {name=p8 lab=ZZ[8]}
|
||||
C {lab_pin.sym} 180 -680 0 0 {name=l30 sig_type=std_logic lab=AA[3:0]}
|
||||
C {lab_pin.sym} 180 -720 0 0 {name=l31 sig_type=std_logic lab=RRSSTT}
|
||||
C {lab_pin.sym} 180 -700 0 0 {name=l32 sig_type=std_logic lab=CCKK}
|
||||
|
|
@ -310,66 +296,66 @@ C {ipin.sym} 100 -80 0 0 { name=p9 lab=RRSSTT }
|
|||
C {ipin.sym} 100 -100 0 0 { name=p10 lab=CCKK }
|
||||
C {ipin.sym} 100 -120 0 0 { name=p11 lab=BB }
|
||||
C {ipin.sym} 100 -140 0 0 { name=p12 lab=AA[3:0] }
|
||||
C {opin.sym} 270 -120 0 0 { name=p13 lab=ZZ[22..1]}
|
||||
C {opin.sym} 270 -120 0 0 { name=p13 lab=ZZ[22:1]}
|
||||
C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"}
|
||||
C {lab_pin.sym} 1410 -620 0 1 {name=p8 lab=ZZ9}
|
||||
C {lab_pin.sym} 1410 -620 0 1 {name=p8 lab=ZZ[9]}
|
||||
C {doublepin.sym} 1110 -460 0 0 {name=x10
|
||||
net_name=true}
|
||||
C {doublepin.sym} 810 -460 0 1 {name=x11
|
||||
net_name=true}
|
||||
C {lab_pin.sym} 510 -410 0 1 {name=p7 lab=ZZ12}
|
||||
C {lab_pin.sym} 630 -410 0 0 {name=p8 lab=ZZ11}
|
||||
C {doublepin.sym} 330 -460 0 0 {name=x12
|
||||
C {lab_pin.sym} 440 -410 0 1 {name=p7 lab=ZZ[12]}
|
||||
C {lab_pin.sym} 630 -410 0 0 {name=p8 lab=ZZ[11]}
|
||||
C {doublepin.sym} 260 -460 0 0 {name=x12
|
||||
net_name=true}
|
||||
C {lab_pin.sym} 1290 -410 0 1 {name=p1 lab=ZZ10}
|
||||
C {lab_pin.sym} 1290 -410 0 1 {name=p1 lab=ZZ[10]}
|
||||
C {doublepin.sym} 1370 -1040 0 0 {name=x13
|
||||
net_name=true}
|
||||
C {lab_pin.sym} 1550 -990 0 1 {name=p2 lab=ZZ13}
|
||||
C {lab_pin.sym} 1550 -990 0 1 {name=p2 lab=ZZ[13]}
|
||||
C {lab_pin.sym} 1520 -1050 0 1 {name=l1 sig_type=std_logic lab=AA[3:0]}
|
||||
C {lab_pin.sym} 1520 -1090 0 1 {name=l11 sig_type=std_logic lab=RRSSTT}
|
||||
C {lab_pin.sym} 1520 -1070 0 1 {name=l12 sig_type=std_logic lab=CCKK}
|
||||
C {lab_pin.sym} 1520 -1030 0 1 {name=l13 sig_type=std_logic lab=BB}
|
||||
C {doublepin.sym} 1370 -1300 0 1 {name=x14
|
||||
net_name=true}
|
||||
C {lab_pin.sym} 1190 -1250 0 0 {name=p2 lab=ZZ14}
|
||||
C {lab_pin.sym} 1190 -1250 0 0 {name=p2 lab=ZZ[14]}
|
||||
C {lab_pin.sym} 1520 -1310 0 1 {name=l3 sig_type=std_logic lab=AA[3:0]}
|
||||
C {lab_pin.sym} 1520 -1350 0 1 {name=l11 sig_type=std_logic lab=RRSSTT}
|
||||
C {lab_pin.sym} 1520 -1330 0 1 {name=l12 sig_type=std_logic lab=CCKK}
|
||||
C {lab_pin.sym} 1520 -1290 0 1 {name=l13 sig_type=std_logic lab=BB}
|
||||
C {doublepin.sym} 330 -230 0 0 {name=x17[1:0]
|
||||
net_name=true}
|
||||
C {doublepin.sym} 810 -230 0 1 {name=x16[1:0]
|
||||
C {doublepin.sym} 860 -230 0 1 {name=x16[1:0]
|
||||
net_name=true}
|
||||
C {lab_pin.sym} 510 -180 0 1 {name=p7 lab=ZZ17}
|
||||
C {lab_pin.sym} 630 -180 0 0 {name=p8 lab=ZZ16}
|
||||
C {lab_pin.sym} 510 -180 0 1 {name=p7 lab=ZZ[17]}
|
||||
C {lab_pin.sym} 680 -180 0 0 {name=p8 lab=ZZ[16]}
|
||||
C {doublepin.sym} 1230 -230 0 0 {name=x22[1:0]
|
||||
net_name=true}
|
||||
C {lab_pin.sym} 1410 -180 0 1 {name=p1 lab=ZZ15}
|
||||
C {lab_pin.sym} 1410 -180 0 1 {name=p1 lab=ZZ[15]}
|
||||
C {inv_ngspice.sym} 80 -260 0 0 {name=x18 ROUT=1000 net_name=true}
|
||||
C {inv_ngspice.sym} 140 -450 0 0 {name=x19 ROUT=1000 net_name=true}
|
||||
C {inv_ngspice.sym} 70 -450 0 0 {name=x19 ROUT=1000 net_name=true}
|
||||
C {doublepin.sym} 1590 -460 0 0 {name=x20
|
||||
net_name=true}
|
||||
C {lab_pin.sym} 1770 -310 0 1 {name=p8 lab=ZZ18}
|
||||
C {lab_pin.sym} 1770 -310 0 1 {name=p8 lab=ZZ[18]}
|
||||
C {doublepin.sym} 1890 -460 0 0 {name=x21
|
||||
net_name=true}
|
||||
C {lab_pin.sym} 2070 -310 0 1 {name=p8 lab=ZZ19}
|
||||
C {inv_ngspice.sym} 720 -350 0 0 {name=x15 ROUT=1000 net_name=true}
|
||||
C {lab_pin.sym} 2070 -310 0 1 {name=p8 lab=ZZ[19]}
|
||||
C {inv_ngspice.sym} 770 -350 0 0 {name=x15 ROUT=1000 net_name=true}
|
||||
C {doublepin.sym} 1410 -870 0 0 {name=x23
|
||||
net_name=true}
|
||||
C {lab_wire.sym} 1180 -880 0 0 {name=l2 sig_type=std_logic lab=AA[3:0]}
|
||||
C {lab_pin.sym} 1590 -820 0 1 {name=p5 lab=ZZ20}
|
||||
C {lab_pin.sym} 1590 -820 0 1 {name=p5 lab=ZZ[20]}
|
||||
C {lab_wire.sym} 1180 -920 0 0 {name=l3 sig_type=std_logic lab=RRSSTT}
|
||||
C {lab_wire.sym} 1180 -900 0 0 {name=l4 sig_type=std_logic lab=CCKK}
|
||||
C {lab_wire.sym} 1180 -860 0 0 {name=l5 sig_type=std_logic lab=BB}
|
||||
C {doublepin.sym} 1910 -870 0 1 {name=x24
|
||||
net_name=true}
|
||||
C {lab_pin.sym} 1730 -820 0 0 {name=p5 lab=ZZ21}
|
||||
C {cross.sym} 1900 -1370 0 0 {name=x25}
|
||||
C {cross.sym} 2140 -1290 0 0 {name=x26}
|
||||
C {cross.sym} 1860 -1070 0 0 {name=x27}
|
||||
C {cross.sym} 2020 -1070 0 0 {name=x28}
|
||||
C {cross.sym} 2180 -990 0 0 {name=x29}
|
||||
C {lab_pin.sym} 1730 -820 0 0 {name=p5 lab=ZZ[21]}
|
||||
C {xcross.sym} 1900 -1370 0 0 {name=x25}
|
||||
C {xcross.sym} 2140 -1290 0 0 {name=x26}
|
||||
C {xcross.sym} 1860 -1070 0 0 {name=x27}
|
||||
C {xcross.sym} 2020 -1070 0 0 {name=x28}
|
||||
C {xcross.sym} 2180 -990 0 0 {name=x29}
|
||||
C {doublepin.sym} 2510 -980 0 1 {name=x30
|
||||
net_name=true}
|
||||
C {lab_pin.sym} 2330 -930 0 0 {name=p5 lab=ZZ22}
|
||||
C {cross.sym} 2060 -1410 2 0 {name=x31}
|
||||
C {lab_pin.sym} 2330 -930 0 0 {name=p5 lab=ZZ[22]}
|
||||
C {xcross.sym} 2060 -1410 2 0 {name=x31}
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
v {xschem version=3.0.0 file_version=1.2 }
|
||||
v {xschem version=3.1.0 file_version=1.2
|
||||
}
|
||||
G {
|
||||
|
||||
process(data, CEN, OEN) begin
|
||||
|
|
@ -148,7 +149,7 @@ library ieee;
|
|||
C {arch_declarations.sym} 750 -630 0 0 { constant RAM_DEPTH :integer := 2**dim;
|
||||
|
||||
|
||||
type RAM is array (integer range <>)of std_logic_vector (width-1 downto 0);
|
||||
signal mem : RAM (0 to RAM_DEPTH-1);
|
||||
type RAMARR is array (integer range <>)of std_logic_vector (width-1 downto 0);
|
||||
signal mem : RAMARR (0 to RAM_DEPTH-1);
|
||||
signal data : std_logic_vector(width-1 downto 0);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2,6 +2,8 @@ v {xschem version=3.1.0 file_version=1.2
|
|||
}
|
||||
G {}
|
||||
K {type=subcircuit
|
||||
verilog_primitive=true
|
||||
verilog_format="assign #90 @@Y = ~@@A ;"
|
||||
format="@name @pinlist @symname ROUT=@ROUT"
|
||||
template="name=x1 ROUT=1000"
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue