fix repeated character in RE, fix changed syntax in verilog example

src/parselabel.l

@@ -130,7 +130,7 @@ const char *expandlabel(const char *s, int *m)
 %x rest
 
 
-ID [-#+_\\/=a-zA-Z0-9]*[-#@+/_\\/=a-zA-Z]+[-#@+_\\/=a-zA-Z0-9]*
+ID [-#+_\\/=a-zA-Z0-9]*[-#@+_\\/=a-zA-Z]+[-#@+_\\/=a-zA-Z0-9]*
 ID_NUM [-#+_\\/=a-zA-Z0-9]+
 
 ID_EXT ([-~#+/=_a-zA-Z][-~#@\\/:.=_+a-zA-Z0-9]*)|([-~#+/.=_a-zA-Z][-~#@\\/:=_+a-zA-Z0-9]*)

xschem_library/examples/greycnt.sch

@@ -12,7 +12,7 @@ end process;}
 K {}
 V {initial begin
   $dumpfile("dumpfile.vcd");
-  $dumpvars;
+  $dumpvars(0, greycnt);
   A=0;
 end