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xschem/xschem_library/devices
History
Stefan Frederik 314acbabda allow tabs and newlines in graph expressions in addition to spaces; updated example schematics 2022-09-23 02:18:51 +02:00
..
adc_bridge.sym added in the menu the (undocumented) "propagate-highlight" function (propagate through conductive elements) 2021-01-02 20:33:34 +01:00
ammeter.sym make op backannotation in schematic work also if raw file loaded at hierarchy level > 0 2022-09-21 13:58:01 +02:00
arch_declarations.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
architecture.sym replaced @ character with ? for spice netlist node multiplicity tags, so translate() will not try to expand them, do not print erc warnings for "non electrical" symbols (architecture, package, port_attributes, use, etc), print_spice_element() result string will be forwarded to translate() if enclosed within tcleval(...), so all @vars will be expanded. translate() in turn will forward to tcl_hook() if necessary. 2020-10-14 23:15:05 +02:00
asrc.sym Alt-a in graph annotates schematic with values at cursor b position. Simulation->Live annotate option to automatically update schematic probes if cursor moved. Some improvements and fixes in ngspice_annotate.tcl. Fix xschem setprobe command. Added missing housekeeping_ctx when a new tab is created. housekeeping_ctx: added more variables to sync. 2022-09-18 05:29:16 +02:00
assign.sym added in the menu the (undocumented) "propagate-highlight" function (propagate through conductive elements) 2021-01-02 20:33:34 +01:00
attributes.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
bsource.sym Alt-a in graph annotates schematic with values at cursor b position. Simulation->Live annotate option to automatically update schematic probes if cursor moved. Some improvements and fixes in ngspice_annotate.tcl. Fix xschem setprobe command. Added missing housekeeping_ctx when a new tab is created. housekeeping_ctx: added more variables to sync. 2022-09-18 05:29:16 +02:00
bus_connect.sym devices/ symbol fixes 2020-10-06 03:20:56 +02:00
bus_connect_nolab.sym bus_connect_nolab.sym type set to "show_label" so it will be highlighted when net is highlighted, without needing to set "auto-highlight nets/pins". 2021-02-10 00:49:46 +01:00
capa-2.sym added in the menu the (undocumented) "propagate-highlight" function (propagate through conductive elements) 2021-01-02 20:33:34 +01:00
capa.sym better text positioning (net_name) on some devices/ symbols 2020-10-17 01:07:18 +02:00
cccs.sym "@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols 2020-09-30 00:30:48 +02:00
ccvs.sym "@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols 2020-09-30 00:30:48 +02:00
code.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
code_shown.sym monospaced font in code_shown.sym 2022-08-30 15:54:18 +02:00
conn_3x1.sym allow tEDAx (flattened) netlisting of hierarchical schematics; added pcb/hierarchical_tedax example 2020-11-24 02:54:45 +01:00
conn_4x1.sym removed some redundant calls in prepare_netlist_structs(), no full instance spatial rehash if adding a component, set template name initials for components in devices/ that do not map directly to spice elements to lowercase letters. 2020-10-18 23:58:40 +02:00
conn_6x1.sym added conn_6x1.sym in devices 2021-09-25 01:49:42 +02:00
conn_8x1.sym allow tEDAx (flattened) netlisting of hierarchical schematics; added pcb/hierarchical_tedax example 2020-11-24 02:54:45 +01:00
conn_10x2.sym removed some redundant calls in prepare_netlist_structs(), no full instance spatial rehash if adding a component, set template name initials for components in devices/ that do not map directly to spice elements to lowercase letters. 2020-10-18 23:58:40 +02:00
conn_14x1.sym removed some redundant calls in prepare_netlist_structs(), no full instance spatial rehash if adding a component, set template name initials for components in devices/ that do not map directly to spice elements to lowercase letters. 2020-10-18 23:58:40 +02:00
connect.sym added in the menu the (undocumented) "propagate-highlight" function (propagate through conductive elements) 2021-01-02 20:33:34 +01:00
connector.sym removed some redundant calls in prepare_netlist_structs(), no full instance spatial rehash if adding a component, set template name initials for components in devices/ that do not map directly to spice elements to lowercase letters. 2020-10-18 23:58:40 +02:00
crystal-2.sym added in the menu the (undocumented) "propagate-highlight" function (propagate through conductive elements) 2021-01-02 20:33:34 +01:00
crystal.sym added in the menu the (undocumented) "propagate-highlight" function (propagate through conductive elements) 2021-01-02 20:33:34 +01:00
dac_bridge.sym added in the menu the (undocumented) "propagate-highlight" function (propagate through conductive elements) 2021-01-02 20:33:34 +01:00
delay.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
delay_line.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
device_param_probe.sym fix in spice.awk: do not clobber user or device format generated .save lines (no ?n tag); add devices/device_param_probe.sym 2022-04-30 10:58:15 +02:00
diode.sym mux simulation operator: set "X" instead of "Z" if select not "0" or "1" 2021-09-27 10:56:23 +02:00
flash_cell.sym removed some redundant calls in prepare_netlist_structs(), no full instance spatial rehash if adding a component, set template name initials for components in devices/ that do not map directly to spice elements to lowercase letters. 2020-10-18 23:58:40 +02:00
generic_pin.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
gnd.sym fixed simulation engine, no more bidirectional devices allowed 2021-10-30 03:12:06 +02:00
ind.sym ind.sym artwork 2022-02-21 00:20:21 +01:00
iopin.sym slight resize in pin text size for better look. top frame in insert text dialog does not extend vertically. 2020-10-11 01:38:28 +02:00
ipin.sym slight resize in pin text size for better look. top frame in insert text dialog does not extend vertically. 2020-10-11 01:38:28 +02:00
isource.sym "@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols 2020-09-30 00:30:48 +02:00
isource_arith.sym allow tabs and newlines in graph expressions in addition to spaces; updated example schematics 2022-09-23 02:18:51 +02:00
isource_pwl.sym "@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols 2020-09-30 00:30:48 +02:00
isource_table.sym "@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols 2020-09-30 00:30:48 +02:00
jumper.sym added in the menu the (undocumented) "propagate-highlight" function (propagate through conductive elements) 2021-01-02 20:33:34 +01:00
k.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
lab_generic.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
lab_pin.sym better backannotation info placement in net labels, fixes in translate() for @spice_get_voltage and @spice_get_current, fixes in ngspice_backannotate routines. 2022-09-21 17:24:16 +02:00
lab_show.sym "@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols 2020-09-30 00:30:48 +02:00
lab_wire.sym updated test schematics to use new xschem annotate_op instead of ngspice::annotate 2022-09-21 18:38:53 +02:00
launcher.sym xschem setprop made way faster if "fast" argument is provided. Example "clear probes" launcher object in mos_power_ampli.sch. 2020-10-19 02:07:17 +02:00
led.sym allow tEDAx (flattened) netlisting of hierarchical schematics; added pcb/hierarchical_tedax example 2020-11-24 02:54:45 +01:00
netlist.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
netlist_at_end.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
netlist_not_shown.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
netlist_not_shown_at_end.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
netlist_options.sym allow tEDAx (flattened) netlisting of hierarchical schematics; added pcb/hierarchical_tedax example 2020-11-24 02:54:45 +01:00
ngspice_get_expr.sym example schematic updated and improvements 2021-01-01 04:24:57 +01:00
ngspice_get_value.sym example schematic updated and improvements 2021-01-01 04:24:57 +01:00
ngspice_probe.sym updated example schematics to new annotate / raw file loading methods 2022-09-20 18:25:31 +02:00
nmos-sub.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
nmos.sym update window title/icon title when switching in tabbed interface 2022-01-10 03:00:33 +01:00
nmos3.sym "@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols 2020-09-30 00:30:48 +02:00
nmos4.sym add missing braces in update recent file submenu, fix file selector improperly setting main window title, added logic/test_mos_verilog.sch depletion mode verilog example 2021-11-20 23:44:19 +01:00
nmos4_depl.sym added devices/rnmos4.sym for enhancement load nmos gate simulation in verilog, updated test_mos_verilog.sch example 2021-12-01 14:25:27 +01:00
noconn.sym optimize unselect_all() 2020-09-30 02:53:20 +02:00
npn.sym allow tEDAx (flattened) netlisting of hierarchical schematics; added pcb/hierarchical_tedax example 2020-11-24 02:54:45 +01:00
opin.sym slight resize in pin text size for better look. top frame in insert text dialog does not extend vertically. 2020-10-11 01:38:28 +02:00
package.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
package_not_shown.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
param.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
param_agauss.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
parax_cap.sym devices/ symbol fixes 2020-10-06 03:20:56 +02:00
pmos-sub.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
pmos.sym fix pcb_current_protection_embed.sch with up to date embedded symbols (previous had very old symbols with errors), fix pmos.sym (make pin names and verilog_format string consistent). All other schematics with embedded symbols updated with current library symbol. Some code in place for saving/restoring symbols in in-memory undo. This code is not compiled so does not affect xschem operation at all. 2021-11-25 04:00:01 +01:00
pmos3.sym "@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols 2020-09-30 00:30:48 +02:00
pmos4.sym add "xschem check_symbols" and "xschem reload_symbols" for future checking of symbols that are newer wrt to schematic. set mtime of newly created schematic (that does not exist on disk) to current time. Add verilog attributes to devices/pmos4.sym 2021-11-21 12:28:36 +01:00
pmoshv4.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
pmosnat.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
pnp.sym added in the menu the (undocumented) "propagate-highlight" function (propagate through conductive elements) 2021-01-02 20:33:34 +01:00
port_attributes.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
res.sym added conn_6x1.sym in devices 2021-09-25 01:49:42 +02:00
res3.sym add devices/res3.sym for generic semiconductor resistance. User must provide a 3-terminal subcircuit for this 2022-07-29 09:40:17 +02:00
res_ac.sym reverted xcb since text quality is slightly better 2022-01-18 03:37:54 +01:00
rgb_led.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
rnmos4.sym swap s/d in verilog netlisting rule for enhancement load "rnmos4.sym" so it can be used as usually done with nmos devices (drain side up) . 2021-12-01 15:53:14 +01:00
simulator_commands.sym added "devices/simulator_commands*.sym" to conditionally include commands in the netlist depending on selected target simulator 2022-09-09 13:06:11 +02:00
simulator_commands_shown.sym added "devices/simulator_commands*.sym" to conditionally include commands in the netlist depending on selected target simulator 2022-09-09 13:06:11 +02:00
spice_probe.sym better backannotation info placement in net labels, fixes in translate() for @spice_get_voltage and @spice_get_current, fixes in ngspice_backannotate routines. 2022-09-21 17:24:16 +02:00
spice_probe_vdiff.sym fixed a potential parse error in edit_prop if list_tokens returns a non list due to malformed input. Added @spice_get_diff_voltage to get a voltage difference between 2 nodes. 2022-09-22 17:35:14 +02:00
sqwsource.sym sqwsource: do not use tcleval, leave the simple expressions parsing to the simulator 2020-10-26 02:58:29 +01:00
switch.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
switch_ngspice.sym "@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols 2020-09-30 00:30:48 +02:00
switch_v_xyce.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
title-2.sym when placing components with lock=true set in template attribute allow to move it to its final position like any other unlocked symbol. Code in place in verilog.awk to do bit unblasting in net-> port associations, but not enalbed it for now as icarus verilog does not handle some bus slices (for example if bus slice direction is different from declared bus direction) 2022-06-09 09:32:34 +02:00
title.sym changed @schname to @schname_ext and added @schname that expands to the schematic name containing the instance, with no extension (no .sch) 2022-08-10 08:38:49 +02:00
use.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
var_res.sym added in the menu the (undocumented) "propagate-highlight" function (propagate through conductive elements) 2021-01-02 20:33:34 +01:00
vccs.sym "@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols 2020-09-30 00:30:48 +02:00
vcr.sym Alt-a in graph annotates schematic with values at cursor b position. Simulation->Live annotate option to automatically update schematic probes if cursor moved. Some improvements and fixes in ngspice_annotate.tcl. Fix xschem setprobe command. Added missing housekeeping_ctx when a new tab is created. housekeeping_ctx: added more variables to sync. 2022-09-18 05:29:16 +02:00
vcvs.sym "@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols 2020-09-30 00:30:48 +02:00
vdd.sym fixed simulation engine, no more bidirectional devices allowed 2021-10-30 03:12:06 +02:00
verilog_delay.sch verilog_preprocessor and verilog_timescale now use verilog_format instead of format (which is for spice), corrected verilog_netlist.c; better backslash and quote (") escaping and unescaping when using attribute select combobox; for unquoting use "xschem get_tok tok 2" instead of "xschem get_tok tok 0" + regsub ....(remove backslashes)... 2020-10-10 23:21:23 +02:00
verilog_delay.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
verilog_preprocessor.sym verilog_preprocessor and verilog_timescale now use verilog_format instead of format (which is for spice), corrected verilog_netlist.c; better backslash and quote (") escaping and unescaping when using attribute select combobox; for unquoting use "xschem get_tok tok 2" instead of "xschem get_tok tok 0" + regsub ....(remove backslashes)... 2020-10-10 23:21:23 +02:00
verilog_timescale.sym more consistent get_tok_value() regarding escaping 2020-11-29 01:59:17 +01:00
vsource.sym bypass tcl for voltage and current backannotation in schematic from cursor b positon in graph 2022-09-20 03:12:46 +02:00
vsource_arith.sym added "Annotate operating point" into Simulation menu 2022-09-22 19:47:25 +02:00
vsource_pwl.sym Alt-a in graph annotates schematic with values at cursor b position. Simulation->Live annotate option to automatically update schematic probes if cursor moved. Some improvements and fixes in ngspice_annotate.tcl. Fix xschem setprobe command. Added missing housekeeping_ctx when a new tab is created. housekeeping_ctx: added more variables to sync. 2022-09-18 05:29:16 +02:00
zener.sym allow tEDAx (flattened) netlisting of hierarchical schematics; added pcb/hierarchical_tedax example 2020-11-24 02:54:45 +01:00