Stefan Frederik
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314acbabda
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allow tabs and newlines in graph expressions in addition to spaces; updated example schematics
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2022-09-23 02:18:51 +02:00 |
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Stefan Frederik
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3e2bc9f95e
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added "Annotate operating point" into Simulation menu
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2022-09-22 19:47:25 +02:00 |
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Stefan Frederik
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e61ef2eabf
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fixed a potential parse error in edit_prop if list_tokens returns a non list due to malformed input. Added @spice_get_diff_voltage to get a voltage difference between 2 nodes.
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2022-09-22 17:35:14 +02:00 |
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Stefan Frederik
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6f907b5430
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updated test schematics to use new xschem annotate_op instead of ngspice::annotate
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2022-09-21 18:38:53 +02:00 |
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Stefan Frederik
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9c89a08111
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better backannotation info placement in net labels, fixes in translate() for @spice_get_voltage and @spice_get_current, fixes in ngspice_backannotate routines.
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2022-09-21 17:24:16 +02:00 |
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Stefan Frederik
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931c1520e3
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make op backannotation in schematic work also if raw file loaded at hierarchy level > 0
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2022-09-21 13:58:01 +02:00 |
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Stefan Frederik
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b542186ebd
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updated example schematics to new annotate / raw file loading methods
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2022-09-20 18:25:31 +02:00 |
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Stefan Frederik
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8169196b35
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bypass tcl for voltage and current backannotation in schematic from cursor b positon in graph
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2022-09-20 03:12:46 +02:00 |
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Stefan Frederik
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7abceb3344
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fix regression in ngspice::get_current, simplified voltage reporting in net label symbols
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2022-09-20 00:12:27 +02:00 |
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Stefan Frederik
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53dc7fe3bf
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add backannotation info (as hidden text) in lab_pin.sym, lab_wire.sym, transitioning example schematics from old (push) backannotation model to new pull model.
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2022-09-19 11:22:04 +02:00 |
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Stefan Frederik
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3a10b39299
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fixed current (also hierarchic) reporting in ammeter.sym and vsource.sym)
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2022-09-19 09:45:35 +02:00 |
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Stefan Frederik
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96f80d1d33
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Alt-a in graph annotates schematic with values at cursor b position. Simulation->Live annotate option to automatically update schematic probes if cursor moved. Some improvements and fixes in ngspice_annotate.tcl. Fix xschem setprobe command. Added missing housekeeping_ctx when a new tab is created. housekeeping_ctx: added more variables to sync.
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2022-09-18 05:29:16 +02:00 |
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Stefan Frederik
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d0b02724cf
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simpler ngspice_probe.sym
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2022-09-13 01:33:09 +02:00 |
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Stefan Frederik
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907315191d
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added "devices/simulator_commands*.sym" to conditionally include commands in the netlist depending on selected target simulator
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2022-09-09 13:06:11 +02:00 |
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Stefan Frederik
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5da8f777b2
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monospaced font in code_shown.sym
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2022-08-30 15:54:18 +02:00 |
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Stefan Frederik
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ce4bd4837a
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changed @schname to @schname_ext and added @schname that expands to the schematic name containing the instance, with no extension (no .sch)
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2022-08-10 08:38:49 +02:00 |
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Stefan Frederik
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aa63f0adab
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add devices/res3.sym for generic semiconductor resistance. User must provide a 3-terminal subcircuit for this
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2022-07-29 09:40:17 +02:00 |
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Stefan Frederik
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28cc187b56
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when placing components with lock=true set in template attribute allow to move it to its final position like any other unlocked symbol. Code in place in verilog.awk to do bit unblasting in net-> port associations, but not enalbed it for now as icarus verilog does not handle some bus slices (for example if bus slice direction is different from declared bus direction)
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2022-06-09 09:32:34 +02:00 |
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Stefan Frederik
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eff273dd08
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fix in spice.awk: do not clobber user or device format generated .save lines (no ?n tag); add devices/device_param_probe.sym
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2022-04-30 10:58:15 +02:00 |
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Stefan Frederik
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a2b0718a7a
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added some symbols
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2022-04-10 09:05:17 +02:00 |
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Stefan Frederik
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77be19bc6a
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ind.sym artwork
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2022-02-21 00:20:21 +01:00 |
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Stefan Frederik
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2e8bd72faf
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reverted xcb since text quality is slightly better
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2022-01-18 03:37:54 +01:00 |
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Stefan Frederik
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19398e8162
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update window title/icon title when switching in tabbed interface
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2022-01-10 03:00:33 +01:00 |
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Stefan Frederik
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756a7ba06d
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swap s/d in verilog netlisting rule for enhancement load "rnmos4.sym" so it can be used as usually done with nmos devices (drain side up) .
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2021-12-01 15:53:14 +01:00 |
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Stefan Frederik
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dcb37ef295
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added devices/rnmos4.sym for enhancement load nmos gate simulation in verilog, updated test_mos_verilog.sch example
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2021-12-01 14:25:27 +01:00 |
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Stefan Frederik
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39a27e856e
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fix pcb_current_protection_embed.sch with up to date embedded symbols (previous had very old symbols with errors), fix pmos.sym (make pin names and verilog_format string consistent). All other schematics with embedded symbols updated with current library symbol. Some code in place for saving/restoring symbols in in-memory undo. This code is not compiled so does not affect xschem operation at all.
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2021-11-25 04:00:01 +01:00 |
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Stefan Frederik
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7f9ee9fc2a
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add "xschem check_symbols" and "xschem reload_symbols" for future checking of symbols that are newer wrt to schematic. set mtime of newly created schematic (that does not exist on disk) to current time. Add verilog attributes to devices/pmos4.sym
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2021-11-21 12:28:36 +01:00 |
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Stefan Frederik
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0e91351e4a
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fix depletion mos example
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2021-11-21 01:18:12 +01:00 |
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Stefan Frederik
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64586f0c2d
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depletion nmos transistor drawn with drain side low as this is the way it is used
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2021-11-21 00:02:48 +01:00 |
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Stefan Frederik
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10114ec838
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add missing braces in update recent file submenu, fix file selector improperly setting main window title, added logic/test_mos_verilog.sch depletion mode verilog example
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2021-11-20 23:44:19 +01:00 |
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Stefan Frederik
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ebf0f0cf95
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fixed simulation engine, no more bidirectional devices allowed
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2021-10-30 03:12:06 +02:00 |
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Stefan Frederik
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0070498eb4
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avoid printing "**** end_element" in spice netlist if current instance is skipped (no format or spice_ignore set); spice_probe_vdiff.sym will print .save v(n1) v(n2) instead of .save v(n1,n2) since this is how ngspice saves nodes (no differential voltage is saved)
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2021-10-21 00:00:54 +02:00 |
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Stefan Frederik
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e8e56aa025
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mux simulation operator: set "X" instead of "Z" if select not "0" or "1"
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2021-09-27 10:56:23 +02:00 |
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Stefan Frederik
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f00b27d97d
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interrupting xschem digital simulation with "Simulation->Forced stop tcl scripts" was leaving "tclstop" variable set, causing following simulation to produce erroneousr results. Any new sim resets the flag to 0.
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2021-09-25 16:16:30 +02:00 |
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Stefan Frederik
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96c84c15f9
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added conn_6x1.sym in devices
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2021-09-25 01:49:42 +02:00 |
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Stefan Frederik
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975b1900dc
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bus_connect_nolab.sym type set to "show_label" so it will be highlighted when net is highlighted, without needing to set "auto-highlight nets/pins".
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2021-02-10 00:49:46 +01:00 |
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Stefan Frederik
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cea1069656
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add "mux", "tristate" functions to logic expressions
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2021-01-10 12:53:10 +01:00 |
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Stefan Frederik
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d64c8abb40
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add -pg also in LDFLAGS if --profile is requested; add little more margin in ps page exports
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2021-01-06 00:12:04 +01:00 |
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Stefan Frederik
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cc993bfe44
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added in the menu the (undocumented) "propagate-highlight" function (propagate through conductive elements)
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2021-01-02 20:33:34 +01:00 |
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Stefan Frederik
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1fe6508704
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ngspice_probe type set from "probe" to "ngprobe" to avoid clashes
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2021-01-02 19:44:01 +01:00 |
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Stefan Frederik
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3528634124
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Add Shift-Delete command that selects all nets/labels/probes physically attached to current selected wire segment/label/pin/probe
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2021-01-02 18:56:42 +01:00 |
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Stefan Frederik
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73045ec1cb
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example schematic updated and improvements
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2021-01-01 04:24:57 +01:00 |
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Stefan Frederik
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14ead18ea4
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"propagate_to" attribute for pins renamed to "goto"
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2020-12-30 21:26:58 +01:00 |
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Stefan Frederik
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880286bdb9
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update examples and ngspice_get_value.sym (@descr attribute)
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2020-12-28 23:18:13 +01:00 |
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Stefan Frederik
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c897f230ce
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update label display in ngspice_get_value.sym
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2020-12-28 20:42:44 +01:00 |
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Stefan Frederik
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b71199c5b8
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added "xschem_simulator" sample example directory for trying logic propagation of probed nets
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2020-12-26 19:26:33 +01:00 |
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Stefan Frederik
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1cfea4d1d3
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svg_draw(): do not print unused layer stylesheets, error check when opening file for printing
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2020-12-22 18:31:08 +01:00 |
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Stefan Frederik
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2e18119645
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remove "m=1" in xyce spice netlists as xyce does not handle m param. Translate spice_probe ".save" to xyce ".print tran", handle different hierarchical expansion of voltage/current nodes in xyce for hierarchical ammeter/spice_probe probes
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2020-12-17 18:26:46 +01:00 |
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Stefan Frederik
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eb2d143e77
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more consistent get_tok_value() regarding escaping
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2020-11-29 01:59:17 +01:00 |
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Stefan Frederik
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9c5739b0f2
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allow tEDAx (flattened) netlisting of hierarchical schematics; added pcb/hierarchical_tedax example
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2020-11-24 02:54:45 +01:00 |