xschem/xschem_library
Stefan Frederik ae4b74f2d8 graph axes in engineering notation (20u, 10p, 3k), fix an issue in graph panning with button1 mouse; ngspice:: get_current, get_voltage, get_diff_voltage, get_node embedded into xschem.tcl, to_eng tcl procedure to convert number to engineering form. 2022-09-28 19:14:31 +02:00
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binto7seg add -pg also in LDFLAGS if --profile is requested; add little more margin in ps page exports 2021-01-06 00:12:04 +01:00
devices allow tabs and newlines in graph expressions in addition to spaces; updated example schematics 2022-09-23 02:18:51 +02:00
examples graph axes in engineering notation (20u, 10p, 3k), fix an issue in graph panning with button1 mouse; ngspice:: get_current, get_voltage, get_diff_voltage, get_node embedded into xschem.tcl, to_eng tcl procedure to convert number to engineering form. 2022-09-28 19:14:31 +02:00
gschem_import some parameter checks in xschem commands, global var removal in simulation help window - No use for production yet 2021-11-16 22:28:10 +01:00
logic revert testbench.sch changes 2022-06-14 10:27:30 +02:00
ngspice add Highlight->Select overlapped instances command 2022-09-27 18:35:42 +02:00
pcb tedax example 2022-01-11 14:44:19 +01:00
rom8k better backannotation info placement in net labels, fixes in translate() for @spice_get_voltage and @spice_get_current, fixes in ngspice_backannotate routines. 2022-09-21 17:24:16 +02:00
rulz-r8c33 "@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols 2020-09-30 00:30:48 +02:00
symgen removed unused files 2020-08-24 10:01:41 +02:00
viewdraw_import add viewdraw_import example schematic/symbol dir for user evaluation and Viewdraw/DxDesigner import testing 2022-01-15 13:31:45 +01:00
xTAG populating xschem git repo 2020-08-08 15:47:34 +02:00
xschem_simulator added missing symbols 2021-12-19 01:32:19 +01:00
Makefile added "xschem_simulator" sample example directory for trying logic propagation of probed nets 2020-12-26 19:26:33 +01:00