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swap s/d in verilog netlisting rule for enhancement load "rnmos4.sym" so it can be used as usually done with nmos devices (drain side up) .

This commit is contained in:
Stefan Frederik 2021-12-01 15:53:14 +01:00
parent 51e85c2d69
commit 756a7ba06d
2 changed files with 2 additions and 2 deletions
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2
xschem_library/devices/rnmos4.sym
View File

@ -3,7 +3,7 @@ G {}
K {type=nmos
format="@spiceprefix@name @pinlist @model w=@w l=@l @extra m=@m"
template="name=M1 model=nmos w=5u l=0.18u del=0 m=1"
verilog_format="rnmos #@del @name ( @@d , @@s , @@g );"}
verilog_format="rnmos #@del @name ( @@s , @@d , @@g );"}
V {}
S {}
E {}

2
xschem_library/logic/test_mos_verilog.sch
View File

@ -90,4 +90,4 @@ C {vdd.sym} 920 -480 0 0 {name=l17 lab=VDD }
C {lab_pin.sym} 820 -230 0 0 {name=l18 sig_type=std_logic lab=IN verilog_type=reg}
C {lab_pin.sym} 990 -310 0 1 {name=l19 sig_type=std_logic lab=OUT3}
C {gnd.sym} 980 -390 0 0 {name=l20 lab=GND}
C {rnmos4.sym} 900 -390 2 1 {name=M6 model=nmos w=5u l=0.18u m=1 del=10}
C {rnmos4.sym} 900 -390 0 0 {name=M6 model=nmos w=5u l=0.18u m=1 del=10}