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xschem
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add missing braces in update recent file submenu, fix file selector improperly setting main window title, added logic/test_mos_verilog.sch depletion mode verilog example

This commit is contained in:
Stefan Frederik 2021-11-20 23:44:19 +01:00
parent e4f4c75e9a
commit 10114ec838
6 changed files with 102 additions and 15 deletions
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10
src/save.c
View File

@ -1057,9 +1057,7 @@ void load_schematic(int load_symbols, const char *filename, int reset_undo) /* 2
char msg[PATH_MAX+100];
struct stat buf;
int i;
char *top_path;
top_path = xctx->top_path[0] ? xctx->top_path : ".";
xctx->prep_hi_structs=0;
xctx->prep_net_structs=0;
xctx->prep_hash_inst=0;
@ -1081,6 +1079,8 @@ void load_schematic(int load_symbols, const char *filename, int reset_undo) /* 2
} else {
xctx->time_last_modify = 0;
}
if(reset_undo) xctx->prev_set_modify = -1; /* will force set_modify(0) to set window title */
else xctx->prev_set_modify = 0; /* will prevent set_modify(0) from setting window title */
if( (fd=fopen(name,fopen_read_mode))== NULL) {
fprintf(errfp, "load_schematic(): unable to open file: %s, filename=%s\n",
name, filename ? filename : "<NULL>");
@ -1128,12 +1128,6 @@ void load_schematic(int load_symbols, const char *filename, int reset_undo) /* 2
my_snprintf(xctx->sch[xctx->currsch], S(xctx->sch[xctx->currsch]), "%s/%s", pwd_dir, name);
my_strncpy(xctx->current_name, name, S(xctx->current_name));
}
if(has_x) { /* 20161207 moved after if( (fd=..)) */
if(reset_undo) {
Tcl_VarEval(interp, "wm title ", top_path, " \"xschem - [file tail [xschem get schname]]\"", NULL);
Tcl_VarEval(interp, "wm iconname ", top_path, " \"xschem - [file tail [xschem get schname]]\"", NULL);
}
}
if(tclgetboolvar("autotrim_wires")) trim_wires();
update_conn_cues(0, 0);
}

4
src/xinit.c
View File

@ -795,7 +795,7 @@ void preview_window(const char *what, const char *tk_win_path, const char *filen
dbg(1, "------\n");
if(!strcmp(what, "create")) {
dbg(1, "preview_window() create, save ctx\n");
dbg(1, "preview_window() create, save ctx, tk_win_path=%s\n", tk_win_path);
tkpre_window = Tk_NameToWindow(interp, tk_win_path, mainwindow);
Tk_MakeWindowExist(tkpre_window);
pre_window = Tk_WindowId(tkpre_window);
@ -810,7 +810,7 @@ void preview_window(const char *what, const char *tk_win_path, const char *filen
}
my_strdup(117, &current_file, filename);
xctx = NULL; /* reset for preview */
alloc_xschem_data(""); /* alloc data into xctx */
alloc_xschem_data(".dialog"); /* alloc data into xctx */
init_pixdata(); /* populate xctx->fill_type array that is used in create_gc() to set fill styles */
preview_xctx = xctx;
preview_xctx->window = pre_window;

9
src/xschem.tcl
View File

@ -361,6 +361,7 @@ proc load_recent_file {} {
proc update_recent_file {f {topwin {} } } {
global recentfile has_x
# puts "update recent file, f=$f, topwin=$topwin"
set old $recentfile
set recentfile {}
lappend recentfile $f
@ -374,13 +375,14 @@ proc update_recent_file {f {topwin {} } } {
set recentfile [lreplace $recentfile 10 end]
}
write_recent_file
if { [info exists has_x] } setup_recent_menu 0 $topwin
if { [info exists has_x] } setup_recent_menu 1 $topwin
if { [info exists has_x] } {setup_recent_menu 0 $topwin}
if { [info exists has_x] } {setup_recent_menu 1 $topwin}
}
proc write_recent_file {} {
global recentfile USER_CONF_DIR
# puts "write recent file recentfile=$recentfile"
set a [catch {open $USER_CONF_DIR/recent_files w} fd]
if { $a } {
puts "write_recent_file: error opening file $f: $fd"
@ -392,6 +394,7 @@ proc write_recent_file {} {
proc setup_recent_menu { {in_new_window 0} { topwin {} } } {
global recentfile
# puts "setup recent menu in_new_window=$in_new_window"
if {$in_new_window} {
$topwin.menubar.file.menu.recent_new_window delete 0 9
} else {

5
xschem_library/devices/nmos4.sym
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@ -1,8 +1,9 @@
v {xschem version=2.9.8 file_version=1.2}
v {xschem version=3.0.0 file_version=1.2 }
G {}
K {type=nmos
format="@spiceprefix@name @pinlist @model w=@w l=@l @extra m=@m"
template="name=M1 model=nmos w=5u l=0.18u m=1"}
template="name=M1 model=nmos w=5u l=0.18u del=0 m=1"
verilog_format="nmos #@del @name ( @@d , @@s , @@g );"}
V {}
S {}
E {}

33
xschem_library/devices/nmos4_depl.sym Normal file
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@ -0,0 +1,33 @@
v {xschem version=3.0.0 file_version=1.2 }
G {}
K {type=nmos
format="@spiceprefix@name @pinlist @model w=@w l=@l @extra m=@m"
template="name=M1 model=nmos w=5u l=0.18u del=0 m=1"
verilog_format="rnmos #@del @name ( @@d , @@s , @@g );"}
V {}
S {}
E {}
L 4 5 -30 5 30 {}
L 4 10 -20 20 -20 {}
L 4 20 -30 20 -20 {}
L 4 10 20 20 20 {}
L 4 20 20 20 30 {}
L 4 -5 -15 -5 15 {}
L 4 -5 0 -5 5 {}
L 4 -20 0 -12.5 0 {}
L 4 -20 0 -5 0 {}
L 4 15 0 20 0 {}
L 4 10 -5 15 0 {}
L 4 10 5 15 0 {}
B 4 5 -20 10 20 {}
B 5 17.5 -32.5 22.5 -27.5 {name=d dir=inout}
B 5 -22.5 -2.5 -17.5 2.5 {name=g dir=in}
B 5 17.5 27.5 22.5 32.5 {name=s dir=inout}
B 5 17.5 -2.5 22.5 2.5 {name=b dir=in}
T {@w\\/@l\\/@m} 12.5 -18.75 0 0 0.2 0.2 {}
T {@spiceprefix@name} 12.5 7.5 0 0 0.2 0.2 {}
T {D} 25 -27.5 0 0 0.15 0.15 {}
T {@#0:net_name} 25 -42.5 0 0 0.15 0.15 {layer=15}
T {@#2:net_name} 25 32.5 0 0 0.15 0.15 {layer=15}
T {@#1:net_name} -25 -12.5 0 1 0.15 0.15 {layer=15}
T {@#3:net_name} 25 0.625 0 0 0.15 0.15 {layer=15}

56
xschem_library/logic/test_mos_verilog.sch Normal file
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@ -0,0 +1,56 @@
v {xschem version=3.0.0 file_version=1.2 }
G {}
K {}
V {}
S {}
E {}
L 4 530 -350 920 -350 {}
L 4 530 -360 530 -350 {}
L 4 510 -350 530 -360 {}
L 4 510 -350 530 -340 {}
L 4 530 -350 530 -340 {}
T {Drain terminal of depletion
load must be on the output
signal and NOT on supply net.} 610 -430 0 0 0.4 0.4 {}
T {Set netlist mode to 'verilog netlist'
(Options menu), then press 'Netlist'
and 'Simulate' button.
You need to have Icarus verilog installed
Configure the verilog simulator in
Simulation-> Configure simulators and tools'
menu.} 700 -240 0 0 0.4 0.4 {}
T {Trivial Depletion NMOS inverter simulation in verilog} 140 -670 0 0 0.7 0.7 {}
N 450 -430 450 -380 { lab=VDD}
N 450 -430 490 -430 { lab=VDD}
N 490 -470 490 -410 { lab=VDD}
N 490 -380 550 -380 { lab=GND}
N 490 -220 550 -220 { lab=GND}
N 490 -350 490 -250 { lab=OUT}
N 490 -190 490 -150 { lab=GND}
N 390 -220 450 -220 { lab=IN}
N 490 -300 610 -300 { lab=OUT}
C {nmos4.sym} 470 -220 0 0 {name=M1 model=nmos w=5u l=0.18u m=1}
C {nmos4_depl.sym} 470 -380 2 1 {name=M3 model=nmos w=5u l=0.18u m=1}
C {gnd.sym} 550 -380 0 0 {name=l1 lab=GND}
C {gnd.sym} 550 -220 0 0 {name=l2 lab=GND}
C {gnd.sym} 490 -150 0 0 {name=l3 lab=GND value=0}
C {vdd.sym} 490 -470 0 0 {name=l4 lab=VDD value=1}
C {lab_pin.sym} 390 -220 0 0 {name=l5 sig_type=std_logic lab=IN verilog_type=reg}
C {lab_pin.sym} 610 -300 0 1 {name=l6 sig_type=std_logic lab=OUT}
C {verilog_timescale.sym} 0 -520 0 0 {name=s1 timestep="1ps" precision="1ps" }
C {code_shown.sym} 0 -390 0 0 {name=testbench only_toplevel=false value="initial begin
$dumpfile(\\"dumpfile.vcd\\");
$dumpvars(0, test_mos_verilog);
IN = 1;
#100000;
IN = 0;
#100000;
IN = 1;
#100000;
IN = 0;
#100000;
$finish;
end
"}
C {title.sym} 160 -30 0 0 {name=l7 author="Stefan Schippers"}