A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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Stefan Frederik ae4b74f2d8 graph axes in engineering notation (20u, 10p, 3k), fix an issue in graph panning with button1 mouse; ngspice:: get_current, get_voltage, get_diff_voltage, get_node embedded into xschem.tcl, to_eng tcl procedure to convert number to engineering form. 2022-09-28 19:14:31 +02:00
XSchemWin (Joanne) update to be clearer on how to compile xschem (from scratch vs using XSchemWin.sln) on Windows using VS2022. font.sch micro edits 2022-09-28 11:33:48 +02:00
doc updated docs with additional video on graphs and Xyce sim 2022-09-22 13:45:55 +02:00
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src graph axes in engineering notation (20u, 10p, 3k), fix an issue in graph panning with button1 mouse; ngspice:: get_current, get_voltage, get_diff_voltage, get_node embedded into xschem.tcl, to_eng tcl procedure to convert number to engineering form. 2022-09-28 19:14:31 +02:00
tests bypass tcl for voltage and current backannotation in schematic from cursor b positon in graph 2022-09-20 03:12:46 +02:00
xschem_library graph axes in engineering notation (20u, 10p, 3k), fix an issue in graph panning with button1 mouse; ngspice:: get_current, get_voltage, get_diff_voltage, get_node embedded into xschem.tcl, to_eng tcl procedure to convert number to engineering form. 2022-09-28 19:14:31 +02:00
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AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
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README_MacOS.md added notes for MacOS 'Big Sur' builds. 2021-09-26 13:24:51 +02:00
config.h.in remove all xrender and all xcb code, remove detection as well. Fix a couple of potentially uninitialized variables 2022-01-19 00:49:46 +01:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions