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xschem
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verilog_preprocessor and verilog_timescale now use verilog_format instead of format (which is for spice), corrected verilog_netlist.c; better backslash and quote (") escaping and unescaping when using attribute select combobox; for unquoting use "xschem get_tok tok 2" instead of "xschem get_tok tok 0" + regsub ....(remove backslashes)...

This commit is contained in:
Stefan Schippers 2020-10-10 23:21:23 +02:00
parent 31eac64d7a
commit 617d708009
6 changed files with 32 additions and 28 deletions
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5
src/scheduler.c
View File

@ -1199,7 +1199,10 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
char *s=NULL;
Tcl_ResetResult(interp);
if(argc < 4) {Tcl_AppendResult(interp, "Missing arguments", NULL);return TCL_ERROR;}
my_strdup(648, &s, get_tok_value(argv[2], argv[3], 0));
if(argc == 5)
my_strdup(648, &s, get_tok_value(argv[2], argv[3], atoi(argv[4])));
else
my_strdup(648, &s, get_tok_value(argv[2], argv[3], 0));
Tcl_AppendResult(interp, s, NULL);
my_free(649, &s);
}

4
src/verilog_netlist.c
View File

@ -77,7 +77,7 @@ void global_verilog_netlist(int global) /* netlister driver */
my_strdup(105, &type,(inst_ptr[i].ptr+instdef)->type);
if( type && (strcmp(type,"timescale")==0 || strcmp(type,"verilog_preprocessor")==0) )
{
str_tmp = get_tok_value( (inst_ptr[i].ptr+instdef)->prop_ptr ,"format",0);
str_tmp = get_tok_value( (inst_ptr[i].ptr+instdef)->prop_ptr ,"verilog_format",0);
my_strdup(106, &tmp_string, str_tmp);
fprintf(fd, "%s\n", str_tmp ? translate(i, tmp_string) : "(NULL)");
}
@ -394,7 +394,7 @@ void verilog_block_netlist(FILE *fd, int i) /*20081205 */
my_strdup(544, &type,(inst_ptr[j].ptr+instdef)->type);
if( type && ( strcmp(type,"timescale")==0 || strcmp(type,"verilog_preprocessor")==0) )
{
str_tmp = get_tok_value( (inst_ptr[j].ptr+instdef)->prop_ptr ,"format",0);
str_tmp = get_tok_value( (inst_ptr[j].ptr+instdef)->prop_ptr ,"verilog_format",0);
my_strdup(545, &tmp_string, str_tmp);
fprintf(fd, "%s\n", str_tmp ? translate(j, tmp_string) : "(NULL)");
}

30
src/xschem.tcl
View File

@ -2002,7 +2002,7 @@ proc edit_vi_netlist_prop {txtlabel} {
if $tcl_debug<=-1 then {puts "edit_vi_prop{}:\n--------\n$tmp\n---------\n"}
if [string compare $tmp $retval] {
set retval $tmp
regsub -all {\\?"} $retval {\\"} retval
regsub -all {(["\\])} $retval {\\\1} retval
set retval \"${retval}\"
if $tcl_debug<=-1 then {puts "modified"}
set rcode ok
@ -2103,7 +2103,7 @@ proc edit_prop {txtlabel} {
set retval [.dialog.e1 get 1.0 {end - 1 chars}]
if { $selected_tok ne {<ALL>} } {
regsub -all {\\?"} $retval {\\"} retval
regsub -all {(["\\])} $retval {\\\1} retval
set retval \"${retval}\"
set retval [xschem subst_tok $retval_orig $selected_tok $retval]
set selected_tok {<ALL>}
@ -2200,7 +2200,7 @@ proc edit_prop {txtlabel} {
set retval_orig [.dialog.e1 get 1.0 {end - 1 chars}]
} else {
set retval [.dialog.e1 get 1.0 {end - 1 chars}]
regsub -all {\\?"} $retval {\\"} retval
regsub -all {(["\\])} $retval {\\\1} retval
set retval \"${retval}\"
set retval_orig [xschem subst_tok $retval_orig $old_selected_tok $retval]
}
@ -2208,8 +2208,8 @@ proc edit_prop {txtlabel} {
if {$selected_tok eq {<ALL>} } {
set retval $retval_orig
} else {
set retval [xschem get_tok $retval_orig $selected_tok]
regsub -all {\\?"} $retval {"} retval
set retval [xschem get_tok $retval_orig $selected_tok 2]
# regsub -all {\\?"} $retval {"} retval
}
.dialog.e1 delete 1.0 end
.dialog.e1 insert 1.0 $retval
@ -2223,7 +2223,7 @@ proc edit_prop {txtlabel} {
} else {
set retval [.dialog.e1 get 1.0 {end - 1 chars}]
if {$retval ne {}} {
regsub -all {\\?"} $retval {\\"} retval
regsub -all {(["\\])} $retval {\\\1} retval
set retval \"${retval}\"
set retval_orig [xschem subst_tok $retval_orig $old_selected_tok $retval]
}
@ -2231,8 +2231,8 @@ proc edit_prop {txtlabel} {
if {$selected_tok eq {<ALL>} } {
set retval $retval_orig
} else {
set retval [xschem get_tok $retval_orig $selected_tok]
regsub -all {\\?"} $retval {"} retval
set retval [xschem get_tok $retval_orig $selected_tok 2]
# regsub -all {\\?"} $retval {"} retval
}
.dialog.e1 delete 1.0 end
.dialog.e1 insert 1.0 $retval
@ -2321,7 +2321,7 @@ proc text_line {txtlabel clear {preserve_disabled disabled} } {
{
set retval [.dialog.e1 get 1.0 {end - 1 chars}]
if { $selected_tok ne {<ALL>} } {
regsub -all {\\?"} $retval {\\"} retval
regsub -all {(["\\])} $retval {\\\1} retval
set retval \"${retval}\"
set retval [xschem subst_tok $retval_orig $selected_tok $retval]
set selected_tok {<ALL>}
@ -2379,7 +2379,7 @@ proc text_line {txtlabel clear {preserve_disabled disabled} } {
set retval_orig [.dialog.e1 get 1.0 {end - 1 chars}]
} else {
set retval [.dialog.e1 get 1.0 {end - 1 chars}]
regsub -all {\\?"} $retval {\\"} retval
regsub -all {(["\\])} $retval {\\\1} retval
set retval \"${retval}\"
set retval_orig [xschem subst_tok $retval_orig $old_selected_tok $retval]
}
@ -2387,8 +2387,8 @@ proc text_line {txtlabel clear {preserve_disabled disabled} } {
if {$selected_tok eq {<ALL>} } {
set retval $retval_orig
} else {
set retval [xschem get_tok $retval_orig $selected_tok]
regsub -all {\\?"} $retval {"} retval
set retval [xschem get_tok $retval_orig $selected_tok 2]
# regsub -all {\\?"} $retval {"} retval
}
.dialog.e1 delete 1.0 end
.dialog.e1 insert 1.0 $retval
@ -2402,7 +2402,7 @@ proc text_line {txtlabel clear {preserve_disabled disabled} } {
} else {
set retval [.dialog.e1 get 1.0 {end - 1 chars}]
if {$retval ne {}} {
regsub -all {\\?"} $retval {\\"} retval
regsub -all {(["\\])} $retval {\\\1} retval
set retval \"${retval}\"
set retval_orig [xschem subst_tok $retval_orig $old_selected_tok $retval]
}
@ -2410,8 +2410,8 @@ proc text_line {txtlabel clear {preserve_disabled disabled} } {
if {$selected_tok eq {<ALL>} } {
set retval $retval_orig
} else {
set retval [xschem get_tok $retval_orig $selected_tok]
regsub -all {\\?"} $retval {"} retval
set retval [xschem get_tok $retval_orig $selected_tok 2]
# regsub -all {\\?"} $retval {"} retval
}
.dialog.e1 delete 1.0 end
.dialog.e1 insert 1.0 $retval

4
xschem_library/devices/verilog_delay.sch
View File

@ -8,5 +8,5 @@ assign outp = x;
}
S {}
E {}
C {devices/ipin.sym} 60 -50 0 0 {name=p1 lab=inp}
C {devices/opin.sym} 160 -50 0 0 {name=p2 lab=outp verilog_type=wire}
C {ipin.sym} 60 -50 0 0 {name=p1 lab=inp}
C {opin.sym} 160 -50 0 0 {name=p2 lab=outp verilog_type=wire}

9
xschem_library/devices/verilog_preprocessor.sym
View File

@ -1,10 +1,11 @@
v {xschem version=2.9.5_RC5 file_version=1.1}
G {type=verilog_preprocessor
v {xschem version=2.9.8 file_version=1.2}
G {}
K {type=verilog_preprocessor
vhdl_ignore=true
spice_ignore=true
tedax_ignore=true
template="name=s1 string=\\"`include \\\\\\"file\\\\\\"\\""
format="@string"
template="name=s1 string=\\"`include \\\\\\"file\\\\\\"\\""
verilog_format="@string"
}
V {}
S {}

8
xschem_library/devices/verilog_timescale.sym
View File

@ -1,11 +1,11 @@
v {xschem version=2.9.7 file_version=1.2}
G {type=timescale
v {xschem version=2.9.8 file_version=1.2}
G {}
K {type=timescale
spice_ignore=true
vhdl_ignore=true
tedax_ignore=true
template="name=s1 timestep=\\"100ps\\" precision=\\"100ps\\" "
verilog_format="`timescale @timestep\\/@precision"
format="`timescale @timestep\\/@precision"}
verilog_format="`timescale @timestep\\/@precision"}
V {}
S {}
E {}