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xschem
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add "xschem check_symbols" and "xschem reload_symbols" for future checking of symbols that are newer wrt to schematic. set mtime of newly created schematic (that does not exist on disk) to current time. Add verilog attributes to devices/pmos4.sym

This commit is contained in:
Stefan Frederik 2021-11-21 12:28:36 +01:00
parent 608912078f
commit 7f9ee9fc2a
5 changed files with 79 additions and 23 deletions
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3
src/save.c
View File

@ -1079,7 +1079,7 @@ void load_schematic(int load_symbols, const char *filename, int reset_undo) /* 2
if(!stat(name, &buf)) { /* file exists */
xctx->time_last_modify = buf.st_mtime;
} else {
xctx->time_last_modify = 0;
xctx->time_last_modify = time(NULL); /* file does not exist, set mtime to current time */
}
if( (fd=fopen(name,fopen_read_mode))== NULL) {
fprintf(errfp, "load_schematic(): unable to open file: %s, filename=%s\n",
@ -1113,6 +1113,7 @@ void load_schematic(int load_symbols, const char *filename, int reset_undo) /* 2
}
dbg(1, "load_schematic(): %s, returning\n", xctx->sch[xctx->currsch]);
} else {
xctx->time_last_modify = time(NULL); /* no file given, set mtime to current time */
clear_drawing();
for(i=0;;i++) {
if(xctx->netlist_type == CAD_SYMBOL_ATTRS) {

36
src/scheduler.c
View File

@ -170,6 +170,31 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
Tcl_ResetResult(interp);
}
else if(!strcmp(argv[1],"check_symbols"))
{
char sympath[PATH_MAX];
const char *name;
struct stat buf;
cmd_found = 1;
for(i=0;i<xctx->symbols;i++) {
name = xctx->sym[i].name;
if(!strcmp(xctx->file_version,"1.0")) {
my_strncpy(sympath, abs_sym_path(name, ".sym"), S(sympath));
} else {
my_strncpy(sympath, abs_sym_path(name, ""), S(sympath));
}
if(!stat(sympath, &buf)) { /* file exists */
if(xctx->time_last_modify < buf.st_mtime) {
dbg(0, "Warning: symbol %s is newer than schematic\n", sympath);
}
} else { /* not found */
dbg(0, "Warning: symbol %s not found\n", sympath);
}
dbg(0, "symbol %d: %s\n", i, sympath);
}
Tcl_ResetResult(interp);
}
else if(!strcmp(argv[1],"check_unique_names"))
{
cmd_found = 1;
@ -1834,10 +1859,19 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
Tcl_ResetResult(interp);
}
else if(!strcmp(argv[1],"reload_symbols"))
{
cmd_found = 1;
remove_symbols();
link_symbols_to_instances(-1);
draw();
Tcl_ResetResult(interp);
}
else if(!strcmp(argv[1],"remove_symbols"))
{
cmd_found = 1;
if(argc==2) remove_symbols();
remove_symbols();
Tcl_ResetResult(interp);
}

2
src/token.c
View File

@ -285,7 +285,7 @@ int match_symbol(const char *name) /* never returns -1, if symbol not found loa
/* update **s modifying only the token values that are */
/* different between *new and *old */
/* return 1 if s xctx->modified 20081221 */
/* return 1 if s modified 20081221 */
int set_different_token(char **s,const char *new, const char *old, int object, int n)
{
register int c, state=TOK_BEGIN, space;

5
xschem_library/devices/pmos4.sym
View File

@ -1,8 +1,9 @@
v {xschem version=2.9.8 file_version=1.2}
v {xschem version=3.0.0 file_version=1.2 }
G {}
K {type=pmos
format="@spiceprefix@name @pinlist @model w=@w l=@l @extra m=@m"
template="name=M1 model=pmos w=5u l=0.18u m=1"}
template="name=M1 model=pmos w=5u l=0.18u del=0 m=1"
verilog_format="pmos #@del @name ( @@d , @@s , @@g );"}
V {}
S {}
E {}

56
xschem_library/logic/test_mos_verilog.sch
View File

@ -10,25 +10,37 @@ and 'Simulate' button.
You need to have Icarus verilog installed
Configure the verilog simulator in
Simulation-> Configure simulators and tools'
menu.} 700 -240 0 0 0.4 0.4 {}
menu.} 800 -240 0 0 0.4 0.4 {}
T {Trivial Depletion NMOS inverter simulation in verilog} 140 -670 0 0 0.7 0.7 {}
N 490 -470 490 -410 { lab=VDD}
N 490 -380 550 -380 { lab=GND}
N 490 -220 550 -220 { lab=GND}
N 490 -350 490 -250 { lab=OUT}
N 490 -190 490 -150 { lab=GND}
N 390 -220 450 -220 { lab=IN}
N 490 -300 610 -300 { lab=OUT}
N 450 -380 450 -340 { lab=OUT}
N 450 -340 490 -340 { lab=OUT}
C {nmos4.sym} 470 -220 0 0 {name=M1 model=nmos w=5u l=0.18u m=1 del=10}
C {nmos4_depl.sym} 470 -380 0 0 {name=M3 model=nmos w=5u l=0.18u m=1 del=10}
C {gnd.sym} 550 -380 0 0 {name=l1 lab=GND}
C {gnd.sym} 550 -220 0 0 {name=l2 lab=GND}
C {gnd.sym} 490 -150 0 0 {name=l3 lab=GND value=0}
C {vdd.sym} 490 -470 0 0 {name=l4 lab=VDD value=1}
C {lab_pin.sym} 390 -220 0 0 {name=l5 sig_type=std_logic lab=IN verilog_type=reg}
C {lab_pin.sym} 610 -300 0 1 {name=l6 sig_type=std_logic lab=OUT}
T {NMOS
depletion
load} 420 -520 0 0 0.4 0.4 {}
T {CMOS} 710 -520 0 0 0.4 0.4 {}
N 380 -480 380 -420 { lab=VDD}
N 380 -390 440 -390 { lab=GND}
N 380 -230 440 -230 { lab=GND}
N 380 -360 380 -260 { lab=OUT}
N 380 -200 380 -160 { lab=GND}
N 280 -230 340 -230 { lab=IN}
N 380 -310 450 -310 { lab=OUT}
N 340 -390 340 -350 { lab=OUT}
N 340 -350 380 -350 { lab=OUT}
N 650 -480 650 -420 { lab=VDD}
N 650 -230 710 -230 { lab=GND}
N 650 -360 650 -260 { lab=OUT2}
N 650 -200 650 -160 { lab=GND}
N 550 -230 610 -230 { lab=IN}
N 650 -310 720 -310 { lab=OUT2}
N 650 -390 710 -390 { lab=VDD}
N 610 -390 610 -230 { lab=IN}
C {nmos4.sym} 360 -230 0 0 {name=M1 model=nmos w=5u l=0.18u m=1 del=10}
C {nmos4_depl.sym} 360 -390 0 0 {name=M3 model=nmos w=5u l=0.18u m=1 del=10}
C {gnd.sym} 440 -390 0 0 {name=l1 lab=GND}
C {gnd.sym} 440 -230 0 0 {name=l2 lab=GND}
C {gnd.sym} 380 -160 0 0 {name=l3 lab=GND value=0}
C {vdd.sym} 380 -480 0 0 {name=l4 lab=VDD value=1}
C {lab_pin.sym} 280 -230 0 0 {name=l5 sig_type=std_logic lab=IN verilog_type=reg}
C {lab_pin.sym} 450 -310 0 1 {name=l6 sig_type=std_logic lab=OUT}
C {verilog_timescale.sym} 0 -520 0 0 {name=s1 timestep="1ps" precision="1ps" }
C {code_shown.sym} 0 -390 0 0 {name=testbench only_toplevel=false value="initial begin
$dumpfile(\\"dumpfile.vcd\\");
@ -46,3 +58,11 @@ C {code_shown.sym} 0 -390 0 0 {name=testbench only_toplevel=false value="initial
end
"}
C {title.sym} 160 -30 0 0 {name=l7 author="Stefan Schippers"}
C {nmos4.sym} 630 -230 0 0 {name=M2 model=nmos w=5u l=0.18u m=1 del=10}
C {gnd.sym} 710 -230 0 0 {name=l8 lab=GND}
C {gnd.sym} 650 -160 0 0 {name=l9 lab=GND }
C {vdd.sym} 650 -480 0 0 {name=l10 lab=VDD }
C {lab_pin.sym} 550 -230 0 0 {name=l11 sig_type=std_logic lab=IN verilog_type=reg}
C {lab_pin.sym} 720 -310 0 1 {name=l12 sig_type=std_logic lab=OUT2}
C {pmos4.sym} 630 -390 0 0 {name=M4 model=pmos w=5u l=0.18u m=1}
C {vdd.sym} 710 -390 0 0 {name=l13 lab=VDD value=1}