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adc_bridge.sym
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added in the menu the (undocumented) "propagate-highlight" function (propagate through conductive elements)
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2021-01-02 20:33:34 +01:00 |
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ammeter.sym
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added some symbols
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2022-04-10 09:05:17 +02:00 |
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arch_declarations.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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architecture.sym
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replaced @ character with ? for spice netlist node multiplicity tags, so translate() will not try to expand them, do not print erc warnings for "non electrical" symbols (architecture, package, port_attributes, use, etc), print_spice_element() result string will be forwarded to translate() if enclosed within tcleval(...), so all @vars will be expanded. translate() in turn will forward to tcl_hook() if necessary.
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2020-10-14 23:15:05 +02:00 |
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asrc.sym
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"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
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2020-09-30 00:30:48 +02:00 |
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assign.sym
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added in the menu the (undocumented) "propagate-highlight" function (propagate through conductive elements)
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2021-01-02 20:33:34 +01:00 |
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attributes.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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bsource.sym
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"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
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2020-09-30 00:30:48 +02:00 |
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bus_connect.sym
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devices/ symbol fixes
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2020-10-06 03:20:56 +02:00 |
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bus_connect_nolab.sym
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bus_connect_nolab.sym type set to "show_label" so it will be highlighted when net is highlighted, without needing to set "auto-highlight nets/pins".
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2021-02-10 00:49:46 +01:00 |
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capa-2.sym
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added in the menu the (undocumented) "propagate-highlight" function (propagate through conductive elements)
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2021-01-02 20:33:34 +01:00 |
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capa.sym
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better text positioning (net_name) on some devices/ symbols
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2020-10-17 01:07:18 +02:00 |
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cccs.sym
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"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
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2020-09-30 00:30:48 +02:00 |
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ccvs.sym
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"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
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2020-09-30 00:30:48 +02:00 |
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code.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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code_shown.sym
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svg_draw(): do not print unused layer stylesheets, error check when opening file for printing
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2020-12-22 18:31:08 +01:00 |
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conn_3x1.sym
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allow tEDAx (flattened) netlisting of hierarchical schematics; added pcb/hierarchical_tedax example
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2020-11-24 02:54:45 +01:00 |
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conn_4x1.sym
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removed some redundant calls in prepare_netlist_structs(), no full instance spatial rehash if adding a component, set template name initials for components in devices/ that do not map directly to spice elements to lowercase letters.
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2020-10-18 23:58:40 +02:00 |
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conn_6x1.sym
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added conn_6x1.sym in devices
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2021-09-25 01:49:42 +02:00 |
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conn_8x1.sym
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allow tEDAx (flattened) netlisting of hierarchical schematics; added pcb/hierarchical_tedax example
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2020-11-24 02:54:45 +01:00 |
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conn_10x2.sym
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removed some redundant calls in prepare_netlist_structs(), no full instance spatial rehash if adding a component, set template name initials for components in devices/ that do not map directly to spice elements to lowercase letters.
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2020-10-18 23:58:40 +02:00 |
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conn_14x1.sym
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removed some redundant calls in prepare_netlist_structs(), no full instance spatial rehash if adding a component, set template name initials for components in devices/ that do not map directly to spice elements to lowercase letters.
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2020-10-18 23:58:40 +02:00 |
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connect.sym
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added in the menu the (undocumented) "propagate-highlight" function (propagate through conductive elements)
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2021-01-02 20:33:34 +01:00 |
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connector.sym
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removed some redundant calls in prepare_netlist_structs(), no full instance spatial rehash if adding a component, set template name initials for components in devices/ that do not map directly to spice elements to lowercase letters.
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2020-10-18 23:58:40 +02:00 |
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crystal-2.sym
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added in the menu the (undocumented) "propagate-highlight" function (propagate through conductive elements)
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2021-01-02 20:33:34 +01:00 |
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crystal.sym
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added in the menu the (undocumented) "propagate-highlight" function (propagate through conductive elements)
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2021-01-02 20:33:34 +01:00 |
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dac_bridge.sym
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added in the menu the (undocumented) "propagate-highlight" function (propagate through conductive elements)
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2021-01-02 20:33:34 +01:00 |
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delay.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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delay_line.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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device_param_probe.sym
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fix in spice.awk: do not clobber user or device format generated .save lines (no ?n tag); add devices/device_param_probe.sym
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2022-04-30 10:58:15 +02:00 |
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diode.sym
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mux simulation operator: set "X" instead of "Z" if select not "0" or "1"
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2021-09-27 10:56:23 +02:00 |
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flash_cell.sym
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removed some redundant calls in prepare_netlist_structs(), no full instance spatial rehash if adding a component, set template name initials for components in devices/ that do not map directly to spice elements to lowercase letters.
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2020-10-18 23:58:40 +02:00 |
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generic_pin.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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gnd.sym
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fixed simulation engine, no more bidirectional devices allowed
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2021-10-30 03:12:06 +02:00 |
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ind.sym
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ind.sym artwork
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2022-02-21 00:20:21 +01:00 |
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iopin.sym
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slight resize in pin text size for better look. top frame in insert text dialog does not extend vertically.
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2020-10-11 01:38:28 +02:00 |
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ipin.sym
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slight resize in pin text size for better look. top frame in insert text dialog does not extend vertically.
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2020-10-11 01:38:28 +02:00 |
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isource.sym
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"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
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2020-09-30 00:30:48 +02:00 |
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isource_arith.sym
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"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
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2020-09-30 00:30:48 +02:00 |
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isource_pwl.sym
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"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
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2020-09-30 00:30:48 +02:00 |
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isource_table.sym
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"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
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2020-09-30 00:30:48 +02:00 |
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jumper.sym
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added in the menu the (undocumented) "propagate-highlight" function (propagate through conductive elements)
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2021-01-02 20:33:34 +01:00 |
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k.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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lab_generic.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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lab_pin.sym
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"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
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2020-09-30 00:30:48 +02:00 |
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lab_show.sym
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"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
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2020-09-30 00:30:48 +02:00 |
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lab_wire.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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launcher.sym
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xschem setprop made way faster if "fast" argument is provided. Example "clear probes" launcher object in mos_power_ampli.sch.
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2020-10-19 02:07:17 +02:00 |
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led.sym
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allow tEDAx (flattened) netlisting of hierarchical schematics; added pcb/hierarchical_tedax example
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2020-11-24 02:54:45 +01:00 |
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netlist.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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netlist_at_end.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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netlist_not_shown.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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netlist_not_shown_at_end.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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netlist_options.sym
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allow tEDAx (flattened) netlisting of hierarchical schematics; added pcb/hierarchical_tedax example
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2020-11-24 02:54:45 +01:00 |
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ngspice_get_expr.sym
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example schematic updated and improvements
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2021-01-01 04:24:57 +01:00 |
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ngspice_get_value.sym
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example schematic updated and improvements
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2021-01-01 04:24:57 +01:00 |
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ngspice_probe.sym
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ngspice_probe type set from "probe" to "ngprobe" to avoid clashes
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2021-01-02 19:44:01 +01:00 |
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nmos-sub.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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nmos.sym
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update window title/icon title when switching in tabbed interface
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2022-01-10 03:00:33 +01:00 |
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nmos3.sym
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"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
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2020-09-30 00:30:48 +02:00 |
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nmos4.sym
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add missing braces in update recent file submenu, fix file selector improperly setting main window title, added logic/test_mos_verilog.sch depletion mode verilog example
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2021-11-20 23:44:19 +01:00 |
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nmos4_depl.sym
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added devices/rnmos4.sym for enhancement load nmos gate simulation in verilog, updated test_mos_verilog.sch example
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2021-12-01 14:25:27 +01:00 |
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noconn.sym
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optimize unselect_all()
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2020-09-30 02:53:20 +02:00 |
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npn.sym
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allow tEDAx (flattened) netlisting of hierarchical schematics; added pcb/hierarchical_tedax example
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2020-11-24 02:54:45 +01:00 |
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opin.sym
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slight resize in pin text size for better look. top frame in insert text dialog does not extend vertically.
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2020-10-11 01:38:28 +02:00 |
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package.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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package_not_shown.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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param.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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param_agauss.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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parax_cap.sym
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devices/ symbol fixes
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2020-10-06 03:20:56 +02:00 |
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pmos-sub.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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pmos.sym
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fix pcb_current_protection_embed.sch with up to date embedded symbols (previous had very old symbols with errors), fix pmos.sym (make pin names and verilog_format string consistent). All other schematics with embedded symbols updated with current library symbol. Some code in place for saving/restoring symbols in in-memory undo. This code is not compiled so does not affect xschem operation at all.
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2021-11-25 04:00:01 +01:00 |
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pmos3.sym
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"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
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2020-09-30 00:30:48 +02:00 |
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pmos4.sym
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add "xschem check_symbols" and "xschem reload_symbols" for future checking of symbols that are newer wrt to schematic. set mtime of newly created schematic (that does not exist on disk) to current time. Add verilog attributes to devices/pmos4.sym
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2021-11-21 12:28:36 +01:00 |
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pmoshv4.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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pmosnat.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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pnp.sym
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added in the menu the (undocumented) "propagate-highlight" function (propagate through conductive elements)
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2021-01-02 20:33:34 +01:00 |
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port_attributes.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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res.sym
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added conn_6x1.sym in devices
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2021-09-25 01:49:42 +02:00 |
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res_ac.sym
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reverted xcb since text quality is slightly better
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2022-01-18 03:37:54 +01:00 |
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rgb_led.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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rnmos4.sym
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swap s/d in verilog netlisting rule for enhancement load "rnmos4.sym" so it can be used as usually done with nmos devices (drain side up) .
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2021-12-01 15:53:14 +01:00 |
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spice_probe.sym
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remove "m=1" in xyce spice netlists as xyce does not handle m param. Translate spice_probe ".save" to xyce ".print tran", handle different hierarchical expansion of voltage/current nodes in xyce for hierarchical ammeter/spice_probe probes
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2020-12-17 18:26:46 +01:00 |
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spice_probe_vdiff.sym
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avoid printing "**** end_element" in spice netlist if current instance is skipped (no format or spice_ignore set); spice_probe_vdiff.sym will print .save v(n1) v(n2) instead of .save v(n1,n2) since this is how ngspice saves nodes (no differential voltage is saved)
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2021-10-21 00:00:54 +02:00 |
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sqwsource.sym
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sqwsource: do not use tcleval, leave the simple expressions parsing to the simulator
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2020-10-26 02:58:29 +01:00 |
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switch.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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switch_ngspice.sym
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"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
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2020-09-30 00:30:48 +02:00 |
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switch_v_xyce.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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title-2.sym
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when placing components with lock=true set in template attribute allow to move it to its final position like any other unlocked symbol. Code in place in verilog.awk to do bit unblasting in net-> port associations, but not enalbed it for now as icarus verilog does not handle some bus slices (for example if bus slice direction is different from declared bus direction)
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2022-06-09 09:32:34 +02:00 |
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title.sym
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LICENSE cosmetic editing
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2020-10-10 11:49:12 +02:00 |
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use.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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var_res.sym
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added in the menu the (undocumented) "propagate-highlight" function (propagate through conductive elements)
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2021-01-02 20:33:34 +01:00 |
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vccs.sym
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"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
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2020-09-30 00:30:48 +02:00 |
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vcr.sym
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"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
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2020-09-30 00:30:48 +02:00 |
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vcvs.sym
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"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
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2020-09-30 00:30:48 +02:00 |
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vdd.sym
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fixed simulation engine, no more bidirectional devices allowed
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2021-10-30 03:12:06 +02:00 |
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verilog_delay.sch
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verilog_preprocessor and verilog_timescale now use verilog_format instead of format (which is for spice), corrected verilog_netlist.c; better backslash and quote (") escaping and unescaping when using attribute select combobox; for unquoting use "xschem get_tok tok 2" instead of "xschem get_tok tok 0" + regsub ....(remove backslashes)...
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2020-10-10 23:21:23 +02:00 |
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verilog_delay.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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verilog_preprocessor.sym
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verilog_preprocessor and verilog_timescale now use verilog_format instead of format (which is for spice), corrected verilog_netlist.c; better backslash and quote (") escaping and unescaping when using attribute select combobox; for unquoting use "xschem get_tok tok 2" instead of "xschem get_tok tok 0" + regsub ....(remove backslashes)...
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2020-10-10 23:21:23 +02:00 |
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verilog_timescale.sym
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more consistent get_tok_value() regarding escaping
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2020-11-29 01:59:17 +01:00 |
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vsource.sym
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better text positioning (net_name) on some devices/ symbols
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2020-10-17 01:07:18 +02:00 |
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vsource_arith.sym
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"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
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2020-09-30 00:30:48 +02:00 |
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vsource_pwl.sym
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"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
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2020-09-30 00:30:48 +02:00 |
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zener.sym
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allow tEDAx (flattened) netlisting of hierarchical schematics; added pcb/hierarchical_tedax example
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2020-11-24 02:54:45 +01:00 |
28cc187b56