ngspice_probe type set from "probe" to "ngprobe" to avoid clashes

src/hspice_backannotate.tcl

@@ -106,18 +106,18 @@ proc annotate {} {
   for { set i 0 } { $i < $lastinst } {incr i } {
     set name [xschem getprop instance $i name]
     set type [xschem getprop instance $i cell::type]
-    if { $type == "probe"  || $type == "devices/probe"} { 
+    if { $type == "probe"} { 
       set net [xschem instance_net $i p]
       if {[catch {xschem setprop $i voltage [get_voltage $net] fast} err]} {
         puts "1 error : $err net: $net"
       }
     }
-    if { $type == "current_probe"  || $type == "devices/current_probe"} { 
+    if { $type == "current_probe"} { 
       if {[catch {xschem setprop $i current [get_current $name] fast} err]} {
         puts "2 error : $err"
       }
     }
-    if { $type == "differential_probe"  || $type == "devices/differential_probe"} { 
+    if { $type == "differential_probe"} { 
       set netp [xschem instance_net $i p]
       set netm [xschem instance_net $i m]
       if {[catch {xschem setprop $i voltage [get_diff_voltage $netp $netm] fast} err]} {

src/select.c

@@ -47,7 +47,7 @@ static void check_connected_wire(int n)
   for(init_inst_iterator(&ctx, x1, y1, x2, y2); (instptr = inst_iterator_next(&ctx)) ;) {
     k = instptr->n;
     type = (xctx->inst[k].ptr+ xctx->sym)->type;
-    if( type && (IS_LABEL_SH_OR_PIN(type) || !strcmp(type, "probe"))) {
+    if( type && (IS_LABEL_SH_OR_PIN(type) || !strcmp(type, "probe") || !strcmp(type, "ngprobe"))) {
       double rx1, ry1, x0, y0;
       int rot, flip;
       xRect *rct;
@@ -99,7 +99,7 @@ void select_connected_wires(void)
         break;
       case ELEMENT:
         type = (xctx->inst[i].ptr+ xctx->sym)->type;
-        if( type && (IS_LABEL_SH_OR_PIN(type) || !strcmp(type, "probe"))) {
+        if( type && (IS_LABEL_SH_OR_PIN(type) || !strcmp(type, "probe") || !strcmp(type, "ngprobe"))) {
           double rx1, ry1, x0, y0;
           int rot, flip, sqx, sqy;
           xRect *rct;

xschem_library/devices/assign.sym

@@ -1,11 +1,11 @@
 v {xschem version=2.9.9 file_version=1.2 }
 G {}
 K {type=delay
+function0="1"
 verilog_format="assign #@delay @@d =  @@s ;"
 vhdl_format=" @@d <=  @@s after @delay ns;"
 format="@name @pinlist 0"
-template="name=V1 delay=1"
-function0="1"}
+template="name=V1 delay=1"}
 V {}
 S {}
 E {}

xschem_library/devices/ngspice_probe.sym

@@ -1,6 +1,6 @@
 v {xschem version=2.9.9 file_version=1.2 }
 G {}
-K {type=probe
+K {type=ngprobe
 vhdl_ignore=true
 spice_ignore=false
 verilog_ignore=true

xschem_library/examples/xnor.sym

@@ -1,13 +1,13 @@
 v {xschem version=2.9.9 file_version=1.2 }
 G {}
 K {type=subcircuit
+function0="1 2 ^ ~"
 verilog_format="xnor #(@risedel , @falldel ) @name ( @#0 , @#1 , @#2 );"
 vhdl_format = "@@Z <= @@A xnor @@B after 0.1 ns;"
 format="@name @pinlist @symname"
 template="name=x1 risedel=400 falldel=300"
 verilog_primitive=true
 vhdl_primitive=true
-function0="1 2 ^ ~"
 }
 V {}
 S {}