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3,103 Commits 32 Branches 7 Tags
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Commit Graph
271 Commits
Author SHA1 Message Date
Alessandro Comodi ea24401d92 bram-sdp minitest: add --verbose to bit2fasm 
Signed-off-by: Alessandro Comodi <[email protected]>
 2020-03-05 11:08:02 +01:00
Alessandro Comodi d7e2fff2a6 bram-sdp minitest: added minitest to check features of SDP brams 
Signed-off-by: Alessandro Comodi <[email protected]>
 2020-03-04 16:46:58 +01:00
litghost f02800daf5 Merge pull request #1218 from antmicro/ddr-uart-bridge 
Added UART DDR minitest
 2020-02-26 17:13:38 -08:00
Tim 'mithro' Ansell 4fbcbb5c87 minitests/litex*: Fix location of clean_json5.py tool. 
Fixes #1255.

Signed-off-by: Tim 'mithro' Ansell <[email protected]>
 2020-02-24 23:07:48 -08:00
Keith Rothman 1f22d60160 Fix up Makefile dependences. 
Signed-off-by: Keith Rothman <[email protected]>
 2020-02-19 16:34:12 -08:00
Keith Rothman 907a9ee72e Pass MAKEFLAGS to children. 
Signed-off-by: Keith Rothman <[email protected]>
 2020-02-19 16:34:11 -08:00
Keith Rothman 9f839a7a08 Attempt to parallelize 074 for additional parts. 
Signed-off-by: Keith Rothman <[email protected]>
 2020-02-19 16:34:11 -08:00
Keith Rothman 222eefcece Use extract_numbers for sort keys to preserve previous DB output. 
Signed-off-by: Keith Rothman <[email protected]>
 2020-02-18 10:45:22 -08:00
Keith Rothman 89761c1102 Add some sorting to JSON outputs. 
Signed-off-by: Keith Rothman <[email protected]>
 2020-02-18 06:39:20 -08:00
Keith Rothman d95eefc8de Fix some bugs present timing analysis script. 
Signed-off-by: Keith Rothman <[email protected]>
 2020-02-13 13:19:46 -08:00
Alessandro Comodi 2f25a2682c ddr-uart: using same design needed in arch-defs for the ddr test 
Signed-off-by: Alessandro Comodi <[email protected]>
 2020-02-12 10:57:34 +01:00
Alessandro Comodi fb5a88a6b8 uart_ddr: improve sdram test script 
Signed-off-by: Alessandro Comodi <[email protected]>
 2020-02-10 15:00:30 +01:00
Alessandro Comodi 51158fd0b8 uart-ddr: addressed review comments and fixed file locations 
Signed-off-by: Alessandro Comodi <[email protected]>
 2020-02-04 11:10:40 +01:00
Alessandro Comodi 8a7e7664f8 uart_ddr: checking out litex at specific commits 
Signed-off-by: Alessandro Comodi <[email protected]>
 2020-02-03 17:17:35 +01:00
Alessandro Comodi 8736d80af3 run make format 
Signed-off-by: Alessandro Comodi <[email protected]>
 2020-02-03 13:08:15 +01:00
Alessandro Comodi f85e244ac6 Added UART DDR minitest 
Signed-off-by: Alessandro Comodi <[email protected]>
 2020-02-03 12:41:40 +01:00
Alessandro Comodi 4a0ca41077 roi_only: copy tilegrid and tileconn from equivalent part 
005-tilegrid fuzzer cannot run for some parts as some of the IOBs are
not available, therefore the fuzzer exits with errors.

Instead, the tilegrid is copied from the specified equivalent part.

Signed-off-by: Alessandro Comodi <[email protected]>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi 88f7830456 addressed review comments 
Signed-off-by: Alessandro Comodi <[email protected]>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi 7226354bdf fix env variable usage in roi_harness minitest 
Signed-off-by: Alessandro Comodi <[email protected]>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi e44027bcaf Move all part-specific files to dedicated directory 
Signed-off-by: Alessandro Comodi <[email protected]>
 2020-01-24 10:13:33 +01:00
Tomasz Michalak 18acada713 minitests: Add min litex with DDR test 
Signed-off-by: Tomasz Michalak <[email protected]>
 2019-12-11 11:49:25 +01:00
Tomasz Michalak fb96f3fe86 minitests: Add minimal Litex configuration for Arty 
Signed-off-by: Tomasz Michalak <[email protected]>
 2019-12-10 10:02:36 +01:00
litghost 0e8ff9b64e Merge pull request #1157 from antmicro/iostandard_minitest 
Minitest for different IOSTANDARDs
 2019-12-09 11:09:33 -08:00
Maciej Kurc eef8ec93cb Added ignoring of PUDC_B pin. 
Signed-off-by: Maciej Kurc <[email protected]>
 2019-12-09 14:40:35 +01:00
Maciej Kurc 75c6ff27de A minitest for Zynq7 EMIO PS->PL interface. 
Signed-off-by: Maciej Kurc <[email protected]>
 2019-12-03 15:39:13 +01:00
Maciej Kurc 20475bfd6a Review comments. 
Signed-off-by: Maciej Kurc <[email protected]>
 2019-12-03 12:07:04 +01:00
Maciej Kurc d9fc7b3f7e Fixed semicolon 
Signed-off-by: Maciej Kurc <[email protected]>
 2019-12-02 10:34:37 +01:00
Maciej Kurc 0fb79b8753 Fixed bug with diff pair loc-ing. 
Signed-off-by: Maciej Kurc <[email protected]>
 2019-12-02 10:16:21 +01:00
Maciej Kurc c396b0f9cc Added support for differential standards. 
Signed-off-by: Maciej Kurc <[email protected]>
 2019-11-29 16:29:41 +01:00
Maciej Kurc e8b05c6b27 Minitest for different IOSTANDARDs 
Signed-off-by: Maciej Kurc <[email protected]>
 2019-11-29 13:55:14 +01:00
Tim 'mithro' Ansell 7386641d9b Fix trailing white space. 
Signed-off-by: Tim 'mithro' Ansell <[email protected]>
 2019-11-03 15:07:24 -08:00
litghost daf284151c Merge pull request #1119 from antmicro/litex_litedram 
minitests: Add test for Litex DRAM memory interface
 2019-10-30 10:40:01 -07:00
litghost 78cf96be0f Merge pull request #1122 from JakeMercer/whitespace 
Whitespace
 2019-10-29 15:04:39 -07:00
Maciej Kurc 4a6930694f Reworked fuzzer, added README.md 
Signed-off-by: Maciej Kurc <[email protected]>
 2019-10-28 15:59:38 +01:00
Jake Mercer c05b4b0406 MAKE - Format Trailing Whitespace 
Add `make format-trailing-ws`.  This recipe finds all _files_ (not
links) known to Git and uses `sed` to remove trailing whitespace.

Signed-off-by: Jake Mercer <[email protected]>
 2019-10-26 10:04:52 +01:00
Tomasz Michalak 43fe925ff3 minitests: Add test for Litex DRAM memory interface 
Signed-off-by: Tomasz Michalak <[email protected]>
 2019-10-24 14:28:37 +02:00
litghost c94cb0224c Revert "Whitespace" 2019-10-23 14:22:17 -07:00
Jake Mercer bf11f43390 FORMAT - Run make format 
Changes after running `make format`.  Future commits which add
whitespace should be caught by CI at the PR stage.

Signed-off-by: Jake Mercer <[email protected]>
 2019-10-22 19:35:24 +01:00
Leonardo Romor c138c156ed Applied requested changes to use XRAY_UTILS_DIR 
Signed-off-by: Leonardo Romor <[email protected]>
 2019-10-10 19:50:02 +02:00
Leonardo Romor 48755a1128 Updated wrong string path added in syspath before import 
Signed-off-by: Leonardo Romor <[email protected]>
 2019-10-10 19:20:32 +02:00
Tim Ansell ecfd250a28 Merge pull request #1068 from antmicro/litex_readme 
Updated README.md for LiteX minitest
 2019-09-30 10:08:47 +02:00
litghost 22750bc2ce Merge pull request #1058 from antmicro/pll_minitest 
Minitest for PLLE2_ADV
 2019-09-26 10:06:53 -07:00
Maciej Kurc dd26790d65 Updated README.md, added different phase settings to the PLL. 
Signed-off-by: Maciej Kurc <[email protected]>
 2019-09-26 09:47:58 +02:00
Tim Ansell d78b50af8b Merge pull request #1040 from antmicro/fix-sphinx-xref-links 
Fixing documentation cross-reference links
 2019-09-25 10:29:07 -07:00
Maciej Kurc 1f31c98265 Updated README.md 
Signed-off-by: Maciej Kurc <[email protected]>
 2019-09-25 12:13:11 +02:00
Alessandro Comodi 2fab112c71 docs: fixed some READMEs and removed empty .md file generation 
Signed-off-by: Alessandro Comodi <[email protected]>
 2019-09-25 09:54:28 +02:00
Maciej Kurc 32feed6640 Removed BUFR and BUFMR, clock division implemented on logic. 
Signed-off-by: Maciej Kurc <[email protected]>
 2019-09-24 10:45:09 +02:00
Maciej Kurc 31ba200080 Minitest for PLLE2_ADV. 
Signed-off-by: Maciej Kurc <[email protected]>
 2019-09-20 11:20:30 +02:00
Maciej Kurc 2b3ca04914 Removed the need for physical pin loopback. The design now transmitts and receives using the same pins. 
Signed-off-by: Maciej Kurc <[email protected]>
 2019-09-12 15:08:05 +02:00
Maciej Kurc e722712661 Formatting 
Signed-off-by: Maciej Kurc <[email protected]>
 2019-09-12 14:35:37 +02:00