prjxray/minitests
Maciej Kurc dd26790d65 Updated README.md, added different phase settings to the PLL.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-09-26 09:47:58 +02:00
..
clb-bused minitest: clean up folders 2019-01-07 23:31:44 +01:00
clb-carry_cin_cyinit minitest: clean up folders 2019-01-07 23:31:44 +01:00
clb-configs minitest: clean up folders 2019-01-07 23:31:44 +01:00
clb-muxf8 minitest: clean up folders 2019-01-07 23:31:44 +01:00
clkbuf introduce vivado wrapper 2018-12-28 19:05:49 +01:00
eccbits introduce vivado wrapper 2018-12-28 19:05:49 +01:00
fixedpnr introduce vivado wrapper 2018-12-28 19:05:49 +01:00
iserdes.idelay Code polish 2019-09-03 16:36:07 +02:00
iserdes.sdr_ddr Removed the need for physical pin loopback. The design now transmitts and receives using the same pins. 2019-09-12 15:08:05 +02:00
litex Update HCLK_IOI offset to match tilegrid 2019-07-26 17:18:48 -07:00
lvb_long_mux introduce vivado wrapper 2018-12-28 19:05:49 +01:00
nodes_wires_list tcl: reformat existing code 2018-12-05 16:52:56 -08:00
oserdes OSERDES minitest without the need for hardware loopbacks. 2019-09-11 13:34:07 +02:00
partial_reconfig_flow introduce vivado wrapper 2018-12-28 19:05:49 +01:00
picorv32-v introduce vivado wrapper 2018-12-28 19:05:49 +01:00
picorv32-y introduce vivado wrapper 2018-12-28 19:05:49 +01:00
pip-switchboxes minitest: clean up folders 2019-01-07 23:31:44 +01:00
plle2_adv Updated README.md, added different phase settings to the PLL. 2019-09-26 09:47:58 +02:00
roi_harness Fix D9/B8 in arty-swbut harness. 2019-07-10 17:15:18 -07:00
srl Added generation of sorted and "uniqued" FASM output 2019-07-05 12:03:30 +02:00
tiles_wires_pips introduce vivado wrapper 2018-12-28 19:05:49 +01:00
timing Add README for timing minitest. 2019-05-29 15:05:18 -07:00
util introduce vivado wrapper 2018-12-28 19:05:49 +01:00