mirror of https://github.com/openXC7/prjxray.git
bram-sdp minitest: added minitest to check features of SDP brams
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
This commit is contained in:
parent
418063afdc
commit
d7e2fff2a6
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@ -0,0 +1,7 @@
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all:
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mkdir -p build
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cd build && bash ../runme.sh
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clean:
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rm -rf build/
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#!/bin/bash
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set -ex
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${XRAY_VIVADO} -mode batch -source ../runme.tcl
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${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o design.bits -z -y design.bit
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test -z "$(fgrep CRITICAL vivado.log)"
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${XRAY_SEGPRINT} -z -D design.bits > design.txt
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${XRAY_BIT2FASM} design.bit > design.fasm
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog ../top.v
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synth_design -top top -flatten_hierarchy none
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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place_design
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route_design
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set_property IS_ENABLED 0 [get_drc_checks {NSTD-1}]
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set_property IS_ENABLED 0 [get_drc_checks {UCIO-1}]
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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@ -0,0 +1,126 @@
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module top (
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);
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// Both RAMB18 in the same tile
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(* KEEP, DONT_TOUCH, LOC="RAMB18_X0Y25" *)
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RAMB18E1 #(
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.RAM_MODE("SDP"),
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.READ_WIDTH_A(36),
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.READ_WIDTH_B(0),
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.WRITE_MODE_A("READ_FIRST"),
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.WRITE_MODE_B("READ_FIRST"),
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.WRITE_WIDTH_A(0),
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.WRITE_WIDTH_B(36)
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) RAMB18E1_BOTH_X1 (
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.ENARDEN(1'b1),
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.ENBWREN(1'b1),
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.REGCEAREGCE(1'b1),
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.REGCEB(1'b0),
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.RSTRAMARSTRAM(1'b1),
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.RSTRAMB(1'b1),
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.RSTREGARSTREG(1'b1),
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.RSTREGB(1'b1),
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.WEA({1'b0}),
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.WEBWE({1'b0})
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);
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(* KEEP, DONT_TOUCH, LOC="RAMB18_X0Y24" *)
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RAMB18E1 #(
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.RAM_MODE("SDP"),
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.READ_WIDTH_A(36),
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.READ_WIDTH_B(0),
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.WRITE_MODE_A("READ_FIRST"),
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.WRITE_MODE_B("READ_FIRST"),
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.WRITE_WIDTH_A(0),
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.WRITE_WIDTH_B(36)
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) RAMB18E1_BOTH_X0 (
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.ENARDEN(1'b1),
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.ENBWREN(1'b1),
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.REGCEAREGCE(1'b1),
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.REGCEB(1'b0),
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.RSTRAMARSTRAM(1'b1),
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.RSTRAMB(1'b1),
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.RSTREGARSTREG(1'b1),
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.RSTREGB(1'b1),
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.WEA({1'b0}),
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.WEBWE({1'b0})
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);
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// ---------------------------------------
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// One RAMB18 in Y0
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(* KEEP, DONT_TOUCH, LOC="RAMB18_X0Y22" *)
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RAMB18E1 #(
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.RAM_MODE("SDP"),
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.READ_WIDTH_A(36),
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.READ_WIDTH_B(0),
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.WRITE_MODE_A("READ_FIRST"),
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.WRITE_MODE_B("READ_FIRST"),
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.WRITE_WIDTH_A(0),
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.WRITE_WIDTH_B(36)
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) RAMB18E1_X0 (
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.ENARDEN(1'b1),
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.ENBWREN(1'b1),
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.REGCEAREGCE(1'b1),
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.REGCEB(1'b0),
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.RSTRAMARSTRAM(1'b1),
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.RSTRAMB(1'b1),
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.RSTREGARSTREG(1'b1),
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.RSTREGB(1'b1),
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.WEA({1'b0}),
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.WEBWE({1'b0})
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);
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// ---------------------------------------
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// One RAMB18 in Y1
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(* KEEP, DONT_TOUCH, LOC="RAMB18_X0Y21" *)
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RAMB18E1 #(
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.RAM_MODE("SDP"),
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.READ_WIDTH_A(36),
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.READ_WIDTH_B(0),
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.WRITE_MODE_A("READ_FIRST"),
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.WRITE_MODE_B("READ_FIRST"),
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.WRITE_WIDTH_A(0),
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.WRITE_WIDTH_B(36)
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) RAMB18E1_X1 (
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.ENARDEN(1'b1),
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.ENBWREN(1'b1),
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.REGCEAREGCE(1'b1),
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.REGCEB(1'b0),
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.RSTRAMARSTRAM(1'b1),
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.RSTRAMB(1'b1),
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.RSTREGARSTREG(1'b1),
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.RSTREGB(1'b1),
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.WEA({1'b0}),
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.WEBWE({1'b0})
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);
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// ---------------------------------------
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// One RAMB36
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(* KEEP, DONT_TOUCH, LOC="RAMB36_X0Y9" *)
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RAMB36E1 #(
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.RAM_MODE("SDP"),
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.READ_WIDTH_A(72),
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.READ_WIDTH_B(0),
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.WRITE_MODE_A("READ_FIRST"),
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.WRITE_MODE_B("READ_FIRST"),
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.WRITE_WIDTH_A(0),
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.WRITE_WIDTH_B(72)
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) RAMB36E1_X0 (
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.ENARDEN(1'b1),
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.ENBWREN(1'b1),
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.REGCEAREGCE(1'b1),
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.REGCEB(1'b0),
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.RSTRAMARSTRAM(1'b1),
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.RSTRAMB(1'b1),
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.RSTREGARSTREG(1'b1),
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.RSTREGB(1'b1),
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.WEA({1'b0}),
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.WEBWE({1'b0})
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);
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endmodule
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