cc7ba29c6b
Added forcing of manual routing through "BB" pips to toggle more bits.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-11-15 12:14:06 +01:00
03b0b9cefc
Added separate clock inputs for PLLs.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-11-15 12:13:49 +01:00
6fd00834b2
Fixed bit names formatting.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-11-14 16:09:44 +01:00
99d31d2e67
071-ppips: skip HCLK_IOI_CK_IGCLK0 ppips addition
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-11-07 15:03:44 +01:00
4cec0817ab
Merge pull request #1080 from JakeMercer/dsp
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DSP - Add Attribute Fuzzing
2019-11-04 08:16:53 -08:00
827081b3b5
hlck-ioi: fix empty list bug in generate.tcl
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-11-04 11:02:52 +01:00
6a3db24da1
FUZZER - DSP - Fixes Following Review
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Signed-off-by: Jake Mercer <jake.mercer@civica.co.uk>
2019-11-02 11:43:12 +00:00
15cfb5bd46
FUZZER - DSP - Add Ports & ROI Module
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Added code for ports to the DSP48E1 instances. Moved DSP instances
inside an ROI module and using the verilog top harness as in other
fuzzers.
Signed-off-by: Jake Mercer <jake.mercer@civica.co.uk>
2019-11-02 11:43:12 +00:00
e0fb0c0cb1
FUZZER - DSP - Refactor
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Refactor the DSP Python scripts to be easier to manage. Use JSON
instead of CSV.
Signed-off-by: Jake Mercer <jake.mercer@civica.co.uk>
2019-11-02 11:43:12 +00:00
596bb27e3b
FUZZER - DSP - Add All Attributes
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Added the rest of the DSP attributes; there are still some issues with mapping the bits.
AREG/BREG mode 2 will require inputs to be connected.
Signed-off-by: Jake Mercer <jmercer04@qub.ac.uk>
2019-11-02 11:43:12 +00:00
8da263c502
FUZZER - DSP - Refactor for Readability & Extensibility
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Signed-off-by: Jake Mercer <jmercer04@qub.ac.uk>
2019-11-02 11:43:12 +00:00
624de250e8
FUZZER - DSP - Cleared Bits
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Changed some tags to be prefixed with 'Z'; these bits are cleared and need the prefix to indicate
the inversion so that they are resolved to the DB correctly.
Signed-off-by: Jake Mercer <jmercer04@qub.ac.uk>
2019-11-02 11:43:12 +00:00
78d64f7558
FUZZER - DSP - Add AUTORESET_PATDET Attribute Fuzzing
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Added fuzzing for the AUTORESET_PATDET attribute of the DSP48 block. Values are RESET_MATCH,
NO_RESET, and RESET_NOT_MATCH; so this can be represented by 2 bits.
Signed-off-by: Jake Mercer <jmercer04@qub.ac.uk>
2019-11-02 11:43:12 +00:00
c575adf8a0
FUZZER - DSP - Add A & B Input Attributes
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Adding `A_INPUT` and `B_INPUT` attribute fuzzing for the DSP48 tiles.
Signed-off-by: Jake Mercer <jmercer04@qub.ac.uk>
2019-11-02 11:43:12 +00:00
13361904ee
hclk-ioi: make 047a dependent on 47 to avoid race condition on piplist
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-10-31 17:00:33 +01:00
949cf722d1
hclk-ioi: re-add IDELAYCTRL to exclude-RE
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-10-31 12:04:43 +01:00
b057e35e73
hclk-ioi: addressed review comments
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-10-31 11:58:11 +01:00
0cf48f337a
hclk-ioi: re-added whole top.py file to avoid having const1
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-10-31 11:58:11 +01:00
1ad84b2b44
hclk-ioi: reduce probability of using lut output as BUFR clock
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-10-31 11:58:11 +01:00
2fb40d0232
hclk-ioi: moved IDELAYCTRL to new parallel fuzzer
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-10-31 11:58:11 +01:00
127022c2a9
hclk-ioi: added IMUX to BEFORE_DIV pips
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-10-31 11:58:11 +01:00
78cf96be0f
Merge pull request #1122 from JakeMercer/whitespace
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Whitespace
2019-10-29 15:04:39 -07:00
b99bd85fa4
Added handling of routing failure in the TCL script.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-10-29 18:20:50 +01:00
0377b5fb4c
Disabled reading PIPs and PPIPs for "R" version of CMT tiles for Zynq7.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-10-29 17:43:10 +01:00
573ee1a38d
Fixed bug in tag_groups.txt
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-10-29 11:55:03 +01:00
bf380f2bdd
PIPs and PPIPs are now not read from the db.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-10-29 11:50:40 +01:00
8267bcdaeb
Updated regex for PIP todo list.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-10-28 15:59:38 +01:00
5ab90a604d
Inceased N
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-10-28 15:59:38 +01:00
355a571400
Removed the INTERNAL_FEEDBACK tag as it is the same as the PLLE2.COMPENSATION.INTENAL
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-10-28 15:59:38 +01:00
4a6930694f
Reworked fuzzer, added README.md
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-10-28 15:59:38 +01:00
73c8652858
Ran make format_py
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-10-28 15:59:38 +01:00
56258694aa
Added rejection of conflicting features.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-10-28 15:59:38 +01:00
f88a1d54b8
Fixed makefile
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-10-28 15:58:58 +01:00
a4250c1487
Comments.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-10-28 15:58:58 +01:00
205bc5c1df
Code formatting.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-10-28 15:58:58 +01:00
89abe7ad47
Modified 034 to manually force routing through specific PIPs and exclude PPIPs from segdata.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-10-28 15:57:22 +01:00
c05b4b0406
MAKE - Format Trailing Whitespace
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Add `make format-trailing-ws`. This recipe finds all _files_ (not
links) known to Git and uses `sed` to remove trailing whitespace.
Signed-off-by: Jake Mercer <jake.mercer@civica.co.uk>
2019-10-26 10:04:52 +01:00
f1f86a02bf
Merge pull request #1118 from antmicro/more_ppips
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Dump PPIPs for additional clock related tiles.
2019-10-25 08:06:36 -07:00
8914753211
run make format
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-10-24 17:45:04 +02:00
7911d78a8f
Removed dumping PPIPs for CLK_BUFG_REBUF.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-10-24 17:42:49 +02:00
04234ec75c
036-ologic: change OSERDESE prefix to OSERDES
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-10-24 17:34:31 +02:00
1d26c91d4a
oserdese: fix wrong fasm prefix
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-10-24 15:56:18 +02:00
a88e73f65e
Added dumping of PPIPs for additional clock routing related tiles.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-10-24 10:20:47 +02:00
97699e4e93
Add HCLK_[LR]_BOT_UTURN aliases.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-10-23 15:30:27 -07:00
c94cb0224c
Revert "Whitespace"
2019-10-23 14:22:17 -07:00
bf11f43390
FORMAT - Run `make format`
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Changes after running `make format`. Future commits which add
whitespace should be caught by CI at the PR stage.
Signed-off-by: Jake Mercer <jake.mercer@civica.co.uk>
2019-10-22 19:35:24 +01:00
c0b8aef3a9
Add pin functions to tilegrid.
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- Add support to emit PUDC_B pullup if unused (for A7 and Z7 fabrics).
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-10-14 16:38:02 -07:00
8813f16bb9
Actually use pin in foreach loop.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-10-07 10:45:19 -07:00
d490b948e8
Add pin functions column to package pins output.
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This is required to know which pin is a PUDC pin, which requires special
handling.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-10-04 15:39:50 -07:00
0922181488
Fixed bits.dbf for 034 to include "0" tags in db.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-09-26 14:38:29 +02:00
Maciej Kurc
Alessandro Comodi
litghost
Jake Mercer
Jake Mercer