Materialisation of the fuzzer tag-group fix f4pga/prjxray#2570 (three
groups under-declared in 035-iob-ilogic; diagnosis by gHashTag): the
four ILOGIC tags whose encoding is all-bits-clear solved to nothing
because dbfixup's group_tags had no group to derive the zero-sides
from. Added per IOI3 variant, segbits + origin_info; masks unchanged:
ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED !26_99 !27_98
ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED !26_29 !27_28
ILOGIC_Y0.IFFDELMUXE3.P1 !28_116
ILOGIC_Y1.IFFDELMUXE3.P1 !29_11
Provenance: fuzzer 035-iob-ilogic re-run with the #2570 groups on
xc7a100tfgg676-1, Vivado ML 2026.1, N=30 specimens, standard
publication pipeline (pushdb, parsedb --strict, sort_db). Gate: the
stock fuzzer under the same environment first regenerated the
committed DDR_CLK_EDGE.{OPPOSITE,SAME}_EDGE and IFFDELMUXE3.P0 lines
byte-identical. Control: the raw segmatch output of the extended run
is byte-identical to the stock run's — tag_groups.txt was the only
variable in the experiment.
This repository is the revision nextpnr-xilinx's submodule records, so
these rows land here first; the same change is filed against
f4pga/prjxray-db as the archival copy. Unblocks the
SAME_EDGE_PIPELINED / IFFDELMUXE3.P1 emission classes
(openXC7/nextpnr-xilinx#114, #65). IDELMUXE3.P2/IFFDELMUXE3.P2 stay
open on purpose: no fuzzer specimen ever selects P2, so they need
top.py/generate.py coverage, not tag grouping.
The bottom-edge RIOI row (k160t RIOI_X73Y9, k325t RIOI_X95Y9) had an
empty bits entry while its neighbours (Y5 offset 10, Y11 offset 22)
carried the CLB_IO_CLK frame map; the k70t X43Y9 confirms the expected
offset 18 (+4 per row). Any routed TQ->T1 pass-through through that
row made fasm2frames abort with FasmLookupError (seen on
litex-ddr-enclustra-kx2).
Single-ended LVCMOS12/15 input on the Y1 (slave) site of an HP-bank
IOB18 tile was missing. nextpnr emits it for LVCMOS15 inputs on the
N pin of a diff pair; fasm2frames failed with FasmLookupError
(blinky/hdmi-stlv7325, RIOB18_X95Y25). Bit value mirrors the
LVCMOS12_LVCMOS15_LVCMOS18.IN variant at the same site, matching the
bit-identity of the Y0 with/without-LVCMOS18 pair (verified in both
families).
RIOB18: IBUFDS_BANK_GLUE, LVDS/SSTL IN_DIFF + IN_ONLY groups,
LVCMOS12_LVCMOS15.IN, LVDS DRIVE/IN_USE, SSTL*.IN_USE, Y1
LVCMOS12_LVCMOS15_SSTL12_SSTL135_SSTL15.IN_ONLY, OBUF_HP_BANK_GLUE
Y0/Y1 and the LVCMOS-family SLEW.SLOW group (LIOB18 mirror).
INT_L/INT_R: IOB_COL_BANK_ACTIVE, IOB_COL_OBUF_CASCADE_Y1.
kintex7 and virtex7 are bit-identical for these tile types (55 shared
RIOB18 + 2020 shared INT_L + 2020 shared INT_R entries, zero
differences), so virtex7 fuzz data transfers directly. Entries
validated with a Vivado 2017.2 golden bitstream on xc7k70tfbg676-2
(IBUFDS input, LVCMOS15/SSTL15 outputs on HP bank 33, SE input):
bitread + bit2fasm decode confirms OBUF_HP_BANK_GLUE, long SLEW.SLOW
group, Y1 IBUF_HP_BANK_GLUE and INT_R IOB_COL bits. Origin tags
record provenance (virtex7-arch-mirror / liob18-arch-mirror).
Unblocks kintex7 open-flow builds using LVDS/diff clocks or HP-bank
pins (previously FasmLookupError in fasm2frames).
Fixes https://github.com/SymbiFlow/prjxray/issues/1803
Updating all based on "Merge pull request #1802 from MidsummerNight/xc7s50"
See [Info File](Info.md) for details.
Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>
Hans Baier
Carlos Venegas Arrabé
Roland Coeurjoly
regymm
Hans Baier
Tim 'mithro' Ansell
Tim 'mithro' Ansell